View XC6VCX130T_3137133.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ds153 (v1.6) february 11, 2011 www.xilinx.com product specification 1 ? 2009?2011 xilinx, inc. xilinx, the xilinx logo, virtex, spartan, ise, and other designated brands included herein are tradema rks of xilinx in the united states and other countries. all other trademarks are the property of their respective owners. general description virtex?-6 cxt fpgas provide designers needing power-optimized 3.75 gb/s transceiver performance with an optimized ratio of built-in system-level blocks. these include 36 kb block ram/fifos, up to 15 mb of block ram, up to 768 dsp48e1 slices, enhanced mixed-mode clock management blocks, pci express? (gen 1) compatible integrated blocks, a tri-mode ethernet media access controller (mac), up to 241k logic cells, and strong ip support. using the third generation asmbl? (advanced silicon modular block) column-b ased architecture, the virtex-6 cxt family also contains selectio? technology with built-in digitally controlled impedance, chipsync? source-synchronous interface blocks, enhanced mixed-mode clock management blocks, and advanced configuration options. customers needing higher transceiver speeds, greater i/o performance, additional ethernet macs, or greater capacity shou ld instead use the virtex-6 lx t or sxt families. built on a 40 nm state-of-the-art copper process technology, virtex-6 cxt fpgas are a programmable alternative to custom asic technology. virtex-6 cxt fpga s are the programmable silicon foundation fo r targeted design platforms that deliver integrated software and hardware components to enable designers to focus on innovation as soon as their development cycle begins. summary of virtex-6 cxt fpga features ? advanced, high-performance, fpga logic ? real 6-input look-up table (lut) technology ? dual lut5 (5-input lut) option ? lut/dual flip-flop pair for applications requiring rich register mix ? improved routing efficiency ? 64-bit (or 32 x 2-bit) distributed lut ram option ? srl32/dual srl16 with registered outputs option ? powerful mixed-mode clock managers (mmcm) ? mmcm blocks provide zero-delay buffering, frequency synthesis, clock-phase shifting, input-jitter filtering, and phase-matched clock division ? 36-kb block ram/fifos ? dual-port ram blocks ? programmable - dual-port widths up to 36 bits - simple dual-port widths up to 72 bits ? enhanced programmable fifo logic ? built-in optional erro r-correction circuitry ? optionally use each block as two independent 18 kb blocks ? high-performance parallel selectio technology ? 1.2 to 2.5v i/o operation ? source-synchronous interfacing using chipsync? technology ? digitally controlled impedance (dci) active termination ? flexible fine-grained i/o banking ? high-speed memory interface support with integrated write-leveling capability ? advanced dsp48e1 slices ? 25 x 18, two's complement multiplier/accumulator ? optional pipelining ? new optional pre-adder to assist filtering applications ? optional bitwise logic functionality ? dedicated cascade connections ? flexible configuration options ? spi and parallel flash interface ? multi-bitstream support with dedicated fallback reconfiguration logic ? automatic bus width detection ? integrated interface blocks for pci express designs ? compliant to the pci express base specification 2.0 ? gen1 endpoint (2.5 gb/s) support with gtx transceivers ? x1, x2, x4, or x8 lane support per block ? one virtual channel, eight traffic classes ? gtx transceivers: 150 mb/s to 3.75 gb/s ? integrated 10/100/1000 mb/s ethernet mac block ? supports 1000base-x pcs/ pma and sgmii using gtx transceivers ? supports mii, gmii, and rgmii using selectio technology resources ? 40 nm copper cmos process technology ? 1.0v core voltage ? two speed grades (-1 and -2) ? two temperature grades (commercial and industrial) ? high signal-integrity flip-chip packaging available in standard or pb-free package options ? compatibility across sub-families: cxt, lxt, and sxt devices are footprint compatible in the same package 52 virtex-6 cxt family data sheet ds153 (v1.6) february 11, 2011 product specification
virtex-6 cxt family data sheet ds153 (v1.6) february 11, 2011 www.xilinx.com product specification 2 virtex-6 cxt fpga feature summary virtex-6 cxt fpga device-packag e combinations and maximum i/os virtex-6 cxt fpga package combinations with the maximum available i/os per package are shown in ta b l e 2 . virtex-6 cxt fpga ordering information the virtex-6 cxt fpga ordering information shown in figure 1 applies to all packages including pb-free. ta bl e 1 : virtex-6 cxt fpga feature summary by device device logic cells configurable logic blocks (clbs) dsp48e1 slices (2) block ram blocks mmcms (4) interface blocks for pci express ethernet macs (5) maximum gtx transceivers total i/o banks (6) max user i/o (7) slices (1) max distributed ram (kb) 18 kb (3) 36 kb max (kb) xc6vcx75t 74,496 11,640 1,045 288 312 156 5,616 6 1 1 12 9 360 XC6VCX130T 128,000 20,000 1,740 480 528 264 9,504 10 2 1 16 15 600 xc6vcx195t 199,680 31,200 3,040 640 688 344 12,384 10 2 1 16 15 600 xc6vcx240t 241,152 37,680 3,650 768 832 416 14,976 12 2 1 16 18 600 notes: 1. each virtex-6 cxt fpga slice contains four luts and eight flip-flops, only some slices can use their luts as distributed ram or srls. 2. each dsp48e1 slice contains a 25 x 18 multiplier, an adder, and an accumulator. 3. block rams are fundamentally 36 kbits in size. each block can also be used as two independent 18 kb blocks. 4. each cmt contains two mixed-mode clock managers (mmcm). 5. this table lists individual ethernet macs per device. 6. does not include configuration bank 0. 7. this number does not include gtx transceivers. ta bl e 2 : virtex-6 cxt fpga device-package combinations and maximum available i/os package ff484 ffg484 ff784 ffg784 ff1156 ffg1156 size(mm) 23x23 29x29 35x35 device gts i/o gts i/o gts i/o xc6vcx75t 8 gtxs 240 12 gtxs 360 XC6VCX130T 8 gtxs 240 12 gtxs 400 16 gtxs 600 xc6vcx195t 12 gtxs 400 16 gtxs 600 xc6vcx240t 12 gtxs 400 16 gtxs 600 notes: 1. flip-chip packages are also available in pb-free versions (ffg). x-ref target - figure 1 figure 1: virtex-6 cxt fpga ordering information example: xc6vcx240t-1ffg1156c device type temper a t u re r a nge: c = commerci a l (t j = 0c to + 8 5c) i = ind us tri a l (t j = ?40c to +100c) n u m b er of pin s p a ck a ge type s peed gr a de (-1, -2) p b -free d s 15 3 _01_062109
virtex-6 cxt family data sheet ds153 (v1.6) february 11, 2011 www.xilinx.com product specification 3 virtex-6 cxt fpga documentation in addition to the data sheet information found herein, complete and up-to-date documentation of the virtex-6 family of fpgas is available on the xilinx we bsite and available for download: virtex-6 fpga configuration guide ( ug360 ) this all-encompassing configuration guide includes chapters on configuration interfaces (serial and parallel), multi-bitstream management, bitstream encryption, boundary-scan and jtag configuration, and reconfiguration techniques. virtex-6 fpga selectio resources user guide ( ug361 ) this guide describes the selectio? resources available in all the virtex-6 cxt devices. virtex-6 fpga clocking resources user guide ( ug362 ) this guide describes the clocking resources available in all the virtex-6 cxt devices, including the mmcm and clock buffers. virtex-6 fpga memory resources user guide ( ug363 ) this guide describes the virtex-6 cxt device block ram and fifo capabilities. virtex-6 fpga clb user guide ( ug364 ) this guide describes the capa bilities of the configurable logic blocks (clb) available in all virtex-6 cxt devices. virtex-6 fpga dsp48e1 slice user guide ( ug369 ) this guide describes the architecture of the dsp48e1 slice in virtex-6 cxt fpgas and provides configuration examples. virtex-6 fpga gtx transceivers user guide ( ug366 ) this guide describes the gtx transceivers available in all the virtex-6 cxt fpgas. virtex-6 fpga tri-mode ethernet mac user guide ( ug368 ) this guide describes the dedicated tri-mode ethernet media access controller (temac) available in all the virtex-6 cxt fpgas. virtex-6 fpga data sheet: dc and switching characteristics ( ds152 ) reference this data sheet when considering device migration to the virtex-6 lxt and sxt families. it contains the dc and switching charac teristic specifications specifically for the virtex-6 lxt and sxt families. virtex-6 fpga packaging and pinout specifications ( ug365 ) these specifications includes the tables for device/package combinations and maximum i/os, pin definitions, pinout tables, pinout diagrams, mechanical drawings, and thermal specifications of the virtex-6 lxt and sxt families. reference these specifications when considering device migration to the virtex-6 lxt and sxt families. configuration bitstream overview for cxt devices this section contains two tables similar to those in the virtex-6 fpga configuration guide only updated for the cxt family. the virtex-6 cxt fpga bitstream contains commands to th e fpga configuration logic as well as configuration data. ta bl e 3 gives a typical bitstream length and ta bl e 4 gives the specific device id codes for the virtex-6 cxt devices. ta bl e 3 : virtex-6 cxt fpga bitstream length device total number of configuration bits xc6vcx75t 26,239,328 XC6VCX130T 43,719,776 xc6vcx195t 61,552,736 xc6vcx240t 73,859,552 ta b l e 4 : virtex-6 cxt fpga device id codes device id code (hex) xc6vcx75t 0x042c4093 XC6VCX130T 0x042ca093 xc6vcx195t 0x042cc093 xc6vcx240t 0x042d0093
virtex-6 cxt family data sheet ds153 (v1.6) february 11, 2011 www.xilinx.com product specification 4 clb overview for cxt devices ta bl e 5 , updated specifically for the cxt fa mily from a similar table in the virtex-6 fpga clb user guide , shows the available resource s in all virtex-6 cxt fpga clbs. regional clock management for cxt devices ta bl e 6 , updated from the virtex-6 fpga clocking resources user guide specifically for the cxt family, shows the number of clock regions in all virtex-6 cxt fpga clbs. cxt packaging specifications ta bl e 7 , updated from the virtex-6 fpga packaging and pinout specifications specifically for the cxt family, shows the number of gtx transceiver i/o channels. ta bl e 8 shows the number of available i/os and the number of differential i/o pairs for each virtex-6 device/package combination. ta bl e 5 : virtex-6 cxt fpga logic resources available in all clbs device total slices slicels slicems number of 6-input luts maximum distributed ram (kb) shift register (kb) number of flip-flops xc6vcx75t 11,640 7,460 4,180 46,560 1045 522.5 93,120 XC6VCX130T 20,000 13,040 6 ,960 80,000 1740 870 160,000 xc6vcx195t 31,200 19,040 12,160 124,800 3140 1570 249,600 xc6vcx240t 37,680 23,080 14,600 150,720 3770 1885 301,440 ta bl e 6 : virtex-6 cxt fpga clock regions device number of clock regions xc6vcx75t 6 XC6VCX130T 10 xc6vcx195t 10 xc6vcx240t 12 ta bl e 7 : number of serial transceivers (gts) i/o channels/device i/o channels device cx75t (1) cx130t (2) cx195t (3) cx240t (4) mgtrxp 8 or 12 8, 12, or 16 12 or 16 12 or 16 mgtrxn 8 or 12 8, 12, or 16 12 or 16 12 or 16 mgttxp 8 or 12 8, 12, or 16 12 or 16 12 or 16 mgttxn 8 or 12 8, 12, or 16 12 or 16 12 or 16 notes: 1. the xc6vcx75t has 8 gtx i/o channels in the ff484/ffg484 package and 12 gtx i/o channels in the ff784/ffg784 package. 2. the XC6VCX130T has 8 gtx i/o channels in the ff484/ffg484 package, 12 gtx i/o channels in the ff784/ffg784 package, and 16 gtx i/o channels in the ff1156/ffg1156 package. 3. the xc6vcx195t has 12 gtx i/o channels in the ff784/ffg784 package and 16 gtx i/o channels in the ff1156/ffg1156 package. 4. the xc6vcx240t has 12 gtx i/o channels in the ff784/ffg784 package and 16 gtx i/o channels in the ff1156/ffg1156 package.
virtex-6 cxt family data sheet ds153 (v1.6) february 11, 2011 www.xilinx.com product specification 5 gtx transceivers in cxt devices cxt devices have between 8 to 16 gigabit transceiver circuits. each gtx transceiver is a combined transmitter and receiver capable of operating at a data rate between 480 mb/s and 3.75 gb/s. lower data rates can be achieved using fpga logic- based oversampling. the transmitter and receiver are independent circuits that use separate plls to multiply the reference frequency input by certain programmable numbers between 2 and 25, to become the bit-serial data clock. each gtx transceiver has a large number of user-definable features and parameters. all of these can be defined during device configuration, and many can also be modified during operation. ta bl e 8 : available i/o pin/device/package combinations virtex-6 cxt device user i/o pins virtex-6 cxt fpga package ff484 ff784 ff1156 xc6vcx75t available user i/os 240 360 ? differential i/o pairs 120 180 ? XC6VCX130T available user i/os 240 400 600 differential i/o pairs 120 200 300 xc6vcx195t available user i/os ? 400 600 differential i/o pairs ? 200 300 xc6vcx240t available user i/os ? 400 600 differential i/o pairs ? 200 300
virtex-6 cxt family data sheet ds153 (v1.6) february 11, 2011 www.xilinx.com product specification 6 ff484 package placement diagrams figure 2 and figure 3 show the placement diagrams for the gtx transceivers in the ff484 package. note: unbonded locations in the ff484 package are: ? cx75t: x0y8, x0y9, x0y10, x0y11 ? cx130t: x0y0, x0y1, x0y2, x0y3, and x0y12, x0y13, x0y14, x0y15 x-ref target - figure 2 figure 2: placement diagram for the ff484 package (1 of 2) cx75t: gtxe1_x0y7 cx1 3 0t: gtxe1_x0y11 cx75t: gtxe1_x0y6 cx1 3 0t: gtxe1_x0y10 quad_115 cx75t: gtxe1_x0y5 cx1 3 0t: gtxe1_x0y9 cx75t: gtxe1_x0y4 cx1 3 0t: gtxe1_x0y 8 b1 b2 d1 d2 c 3 c4 f1 f2 j4 j 3 l4 l 3 e 3 e4 h1 h2 g 3 g4 k1 k2 mgtrxp 3 _115 mgtrxn 3 _115 mgttxp 3 _115 mgttxn 3 _115 mgtrxp2_115 mgtrxn2_115 mgttxp2_115 mgttxn2_115 mgtrefclk1p_115 mgtrefclk1n_115 mgtrefclk0p_115 mgtrefclk0n_115 mgtrxp1_115 mgtrxn1_115 mgttxp1_115 mgttxn1_115 mgtrxp0_115 mgtrxn0_115 mgttxp0_115 mgttxn0_115 d s 15 3 _02_041510 x-ref target - figure 3 figure 3: placement diagram for the ff484 package (2 of 2) cx75t: gtxe1_x0y 3 cx1 3 0t: gtxe1_x0y7 cx75t: gtxe1_x0y2 cx1 3 0t: gtxe1_x0y6 quad_114 cx75t: gtxe1_x0y1 cx1 3 0t: gtxe1_x0y5 cx75t: gtxe1_x0y0 cx1 3 0t: gtxe1_x0y4 w 3 w4 m1 m2 y1 y2 p1 p2 r4 r 3 u4 u 3 aa 3 aa4 t1 t2 ab1 ab2 v1 v2 mgtrxp 3 _114 mgtrxn 3 _114 mgttxp 3 _114 mgttxn 3 _114 mgtrxp2_114 mgtrxn2_114 mgttxp2_114 mgttxn2_114 mgtrefclk1p_114 mgtrefclk1n_114 mgtrefclk0p_114 mgtrefclk0n_114 mgtrxp1_114 mgtrxn1_114 mgttxp1_114 mgttxn1_114 mgtrxp0_114 mgtrxn0_114 mgttxp0_114 mgttxn0_114 d s 15 3 _0 3 _041510
virtex-6 cxt family data sheet ds153 (v1.6) february 11, 2011 www.xilinx.com product specification 7 ff784 package placement diagrams figure 4 through figure 6 show the placement diagrams for the gtx transceivers in the ff784 package. note: unbonded locations in the ff784 package are: ? cx130t: x0y0, x0y1, x0y2, x0y3 ? cx195t: x0y0, x0y1, x0y2, x0y3 ? cx240t: x0y0, x0y1, x0y2, x0y3 x-ref target - figure 4 figure 4: placement diagram for the ff784 package (1 of 3) cx75t: gtxe1_x0y11 cx1 3 0t: gtxe1_x0y15 cx195t: gtxe1_x0y15 cx240t: gtxe1_x0y15 cx75t: gtxe1_x0y10 cx1 3 0t: gtxe1_x0y14 cx195t: gtxe1_x0y14 cx240t: gtxe1_x0y14 quad_116 cx75t: gtxe1_x0y9 cx1 3 0t: gtxe1_x0y1 3 cx195t: gtxe1_x0y1 3 cx240t: gtxe1_x0y1 3 cx75t: gtxe1_x0y 8 cx1 3 0t: gtxe1_x0y12 cx195t: gtxe1_x0y12 cx240t: gtxe1_x0y12 k1 k2 e 3 e4 h1 h2 c 3 c4 j4 j 3 g4 g 3 f1 f2 b1 b2 d1 d2 a 3 a4 mgtrxp 3 _116 mgtrxn 3 _116 mgttxp 3 _116 mgttxn 3 _116 mgtrxp2_116 mgtrxn2_116 mgttxp2_116 mgttxn2_116 mgtrefclk1p_116 mgtrefclk1n_116 mgtrefclk0p_116 mgtrefclk0n_116 mgtrxp1_116 mgtrxn1_116 mgttxp1_116 mgttxn1_116 mgtrxp0_116 mgtrxn0_116 mgttxp0_116 mgttxn0_116 d s 15 3 _04_041510 x-ref target - figure 5 figure 5: placement diagram for the ff784 package (2 of 3) cx75t: gtxe1_x0y7 cx1 3 0t: gtxe1_x0y11 cx195t: gtxe1_x0y11 cx240t: gtxe1_x0y11 cx75t: gtxe1_x0y6 cx1 3 0t: gtxe1_x0y10 cx195t: gtxe1_x0y10 cx240t: gtxe1_x0y10 quad_115 cx75t: gtxe1_x0y5 cx1 3 0t: gtxe1_x0y9 cx195t: gtxe1_x0y9 cx240t: gtxe1_x0y9 cx75t: gtxe1_x0y4 cx1 3 0t: gtxe1_x0y 8 cx195t: gtxe1_x0y 8 cx240t: gtxe1_x0y 8 l 3 l4 m1 m2 n 3 n4 p1 p2 p6 p5 t6 t5 r 3 r4 t1 t2 u 3 u4 v1 v2 mgtrxp 3 _115 mgtrxn 3 _115 mgttxp 3 _115 mgttxn 3 _115 mgtrxp2_115 mgtrxn2_115 mgttxp2_115 mgttxn2_115 mgtrefclk1p_115 mgtrefclk1n_115 mgtrefclk0p_115 mgtrefclk0n_115 mgtrxp1_115 mgtrxn1_115 mgttxp1_115 mgttxn1_115 mgtrxp0_115 mgtrxn0_115 mgttxp0_115 mgttxn0_115 d s 15 3 _05_041510
virtex-6 cxt family data sheet ds153 (v1.6) february 11, 2011 www.xilinx.com product specification 8 x-ref target - figure 6 figure 6: placement diagram for the ff784 package (3 of 3) cx75t: gtxe1_x0y 3 cx1 3 0t: gtxe1_x0y7 cx195t: gtxe1_x0y7 cx240t: gtxe1_x0y7 cx75t: gtxe1_x0y2 cx1 3 0t: gtxe1_x0y6 cx195t: gtxe1_x0y6 cx240t: gtxe1_x0y6 quad_114 cx75t: gtxe1_x0y1 cx1 3 0t: gtxe1_x0y5 cx195t: gtxe1_x0y5 cx240t: gtxe1_x0y5 cx75t: gtxe1_x0y0 cx1 3 0t: gtxe1_x0y4 cx195t: gtxe1_x0y4 cx240t: gtxe1_x0y4 ac 3 ac4 y1 y2 ae 3 ae4 ab1 ab2 w4 w 3 aa4 aa 3 ag 3 ag4 ad1 ad2 ah1 ah2 af1 af2 mgtrxp 3 _114 mgtrxn 3 _114 mgttxp 3 _114 mgttxn 3 _114 mgtrxp2_114 mgtrxn2_114 mgttxp2_114 mgttxn2_114 mgtrefclk1p_114 mgtrefclk1n_114 mgtrefclk0p_114 mgtrefclk0n_114 mgtrxp1_114 mgtrxn1_114 mgttxp1_114 mgttxn1_114 mgtrxp0_114 mgtrxn0_114 mgttxp0_114 mgttxn0_114 d s 15 3 _06_041510
virtex-6 cxt family data sheet ds153 (v1.6) february 11, 2011 www.xilinx.com product specification 9 ff1156 package placement diagrams figure 7 through figure 10 show the placement diagrams for the gtx transceivers in the ff1156 package. x-ref target - figure 7 figure 7: placement diagram for the ff1156 package (1 of 4) cx1 3 0t: gtxe1_x0y15 cx195t: gtxe1_x0y15 cx240t: gtxe1_x0y15 cx1 3 0t: gtxe1_x0y14 cx195t: gtxe1_x0y14 cx240t: gtxe1_x0y14 cx1 3 0t: gtxe1_x0y1 3 cx195t: gtxe1_x0y1 3 cx240t: gtxe1_x0y1 3 cx1 3 0t: gtxe1_x0y12 cx195t: gtxe1_x0y12 cx240t: gtxe1_x0y12 quad_116 b5 b6 a 3 a4 d5 d6 b1 b2 f6 f5 h6 h5 e 3 e4 c 3 c4 g 3 g4 d1 d2 mgtrxp 3 _116 mgtrxn 3 _116 mgttxp 3 _116 mgttxn 3 _116 mgtrxp2_116 mgtrxn2_116 mgttxp2_116 mgttxn2_116 mgtrefclk1p_116 mgtrefclk1n_116 mgtrefclk0p_116 mgtrefclk0n_116 mgtrxp1_116 mgtrxn1_116 mgttxp1_116 mgttxn1_116 mgtrxp0_116 mgtrxn0_116 mgttxp0_116 mgttxn0_116 d s 15 3 _07_020210 x-ref target - figure 8 figure 8: placement diagram for the ff1156 package (2 of 4) cx1 3 0t: gtxe1_x0y11 cx195t: gtxe1_x0y11 cx240t: gtxe1_x0y11 cx1 3 0t: gtxe1_x0y10 cx195t: gtxe1_x0y10 cx240t: gtxe1_x0y10 quad_115 cx1 3 0t: gtxe1_x0y9 cx195t: gtxe1_x0y9 cx240t: gtxe1_x0y9 cx1 3 0t: gtxe1_x0y 8 cx195t: gtxe1_x0y 8 cx240t: gtxe1_x0y 8 j 3 j4 f1 f2 k5 k6 h1 h2 m6 m5 p6 p5 l 3 l4 k1 k2 n 3 n4 m1 m2 mgtrxp 3 _115 mgtrxn 3 _115 mgttxp 3 _115 mgttxn 3 _115 mgtrxp2_115 mgtrxn2_115 mgttxp2_115 mgttxn2_115 mgtrefclk1p_115 mgtrefclk1n_115 mgtrefclk0p_115 mgtrefclk0n_115 mgtrxp1_115 mgtrxn1_115 mgttxp1_115 mgttxn1_115 mgtrxp0_115 mgtrxn0_115 mgttxp0_115 mgttxn0_115 d s 15 3 _0 8 _020210
virtex-6 cxt family data sheet ds153 (v1.6) february 11, 2011 www.xilinx.com product specification 10 x-ref target - figure 9 figure 9: placement diagram for the ff1156 package (3 of 4) cx1 3 0t: gtxe1_x0y7 cx195t: gtxe1_x0y7 cx240t: gtxe1_x0y7 cx1 3 0t: gtxe1_x0y6 cx195t: gtxe1_x0y6 cx240t: gtxe1_x0y6 quad_114 cx1 3 0t: gtxe1_x0y5 cx195t: gtxe1_x0y5 cx240t: gtxe1_x0y5 cx1 3 0t: gtxe1_x0y4 cx195t: gtxe1_x0y4 cx240t: gtxe1_x0y4 r 3 r4 p1 p2 u 3 u4 t1 t2 t6 t5 v6 v5 w 3 w4 v1 v2 aa 3 aa4 y1 y2 mgtrxp 3 _114 mgtrxn 3 _114 mgttxp 3 _114 mgttxn 3 _114 mgtrxp2_114 mgtrxn2_114 mgttxp2_114 mgttxn2_114 mgtrefclk1p_114 mgtrefclk1n_114 mgtrefclk0p_114 mgtrefclk0n_114 mgtrxp1_114 mgtrxn1_114 mgttxp1_114 mgttxn1_114 mgtrxp0_114 mgtrxn0_114 mgttxp0_114 mgttxn0_114 d s 15 3 _09_020210 x-ref target - figure 10 figure 10: placement diagram for the ff1156 package (4 of 4) cx1 3 0t: gtxe1_x0y 3 cx195t: gtxe1_x0y 3 cx240t: gtxe1_x0y 3 cx1 3 0t: gtxe1_x0y2 cx195t: gtxe1_x0y2 cx240t: gtxe1_x0y2 quad_11 3 cx1 3 0t: gtxe1_x0y1 cx195t: gtxe1_x0y1 cx240t: gtxe1_x0y1 cx1 3 0t: gtxe1_x0y0 cx195t: gtxe1_x0y0 cx240t: gtxe1_x0y0 ac 3 ac4 ab1 ab2 ae 3 ae4 ad1 ad2 ab6 ab5 ad6 ad5 af5 af6 af1 af2 ag 3 ag4 ah1 ah2 mgtrxp 3 _11 3 mgtrxn 3 _11 3 mgttxp 3 _11 3 mgttxn 3 _11 3 mgtrxp2_11 3 mgtrxn2_11 3 mgttxp2_11 3 mgttxn2_11 3 mgtrefclk1p_11 3 mgtrefclk1n_11 3 mgtrefclk0p_11 3 mgtrefclk0n_11 3 mgtrxp1_11 3 mgtrxn1_11 3 mgttxp1_11 3 mgttxn1_11 3 mgtrxp0_11 3 mgtrxn0_11 3 mgttxp0_11 3 mgttxn0_11 3 d s 15 3 _10_ 020210
virtex-6 cxt family data sheet ds153 (v1.6) february 11, 2011 www.xilinx.com product specification 11 virtex-6 cxt fpga electrical characteristics introduction virtex-6 cxt fpgas are available in -2 and -1 speed grades, with -2 having the highest performance. virtex-6 cxt fpga dc and ac characteristics are specified for both commercial and industrial grades. except the operating temperature range or unless otherwise noted, all the dc and ac electrical para meters are the same for a particular speed grade (that is, the timing characteristics of a -1 speed grade industrial device are the same as for a -1 speed grade commercial device). however, only selected speed grades and/or devices might be available in the industrial range. all supply voltage and junction temperature specifications are representative of worst-case conditions. the parameters included are common to popular designs and typical applications. all specifications are subject to change without notice. virtex-6 cxt fpga dc characteristics ta bl e 9 : absolute maximum ratings (1) symbol description units v ccint internal supply voltage relative to gnd ?0.5 to 1.1 v v ccaux auxiliary supply voltage relative to gnd ?0.5 to 3.0 v v cco output drivers supply voltage relative to gnd ?0.5 to 3.0 v v batt key memory battery backup supply ?0.5 to 3.0 v v fs external voltage supply for efuse programming (2) ?0.5 to 3.0 v v ref input reference voltage ?0.5 to 3.0 v v in (3) 2.5v or below i/o input voltage relative to gnd (4) (user and dedicate d i/os) ?0.5 to v cco ? 0.5 v v ts voltage applied to 3-state 2.5v or below output (4) (user and dedicated i/os) ?0.5 to v cco ? 0.5 v t stg storage temperature (ambient) ?65 to 150 c t sol maximum soldering temperature (5) ? 220 c t j maximum junction temperature (5) ? 125 c notes: 1. stresses beyond those listed under absolute maximum ratings might cause permanent damage to the device. these are stress rati ngs only, and functional operation of the device at these or any other conditions beyond those listed under operating conditions is not implied. exposure to absolute maximum ratings conditions for extended periods of time might affect device reliability. 2. when not programming efuse, connect v fs to gnd. 3. 2.5v i/o absolute maximum limit applied to dc and ac signals. 4. for i/o operation, refer to the virtex-6 fpga selectio resources user guide . 5. for soldering guidelines and thermal considerations, see virtex-6 fpga packaging and pinout specification .
virtex-6 cxt family data sheet ds153 (v1.6) february 11, 2011 www.xilinx.com product specification 12 ta bl e 1 0 : recommended operating conditions symbol description min max units v ccint internal supply voltag e relative to gnd, t j =0 ? c to +85 ? c0.951.05v internal supply voltag e relative to gnd, t j =?40 ? c to +100 ? c0.951.05v v ccaux auxiliary supply voltage relative to gnd, t j =0 ? c to +85 ? c 2.375 2.625 v auxiliary supply voltage relative to gnd, t j =?40 ? c to +100 ? c 2.375 2.625 v v cco (1)(2)(3) supply voltage relative to gnd, t j =0 ? c to +85 ? c 1.14 2.625 v supply voltage relative to gnd, t j = ?40 ? c to +100 ? c 1.14 2.625 v v in 2.5v supply voltage relative to gnd, t j =0 ? c to +85 ? c gnd ? 0.20 2.625 v 2.5v supply voltage relative to gnd, t j =?40 ? c to +100 ? c gnd ? 0.20 2.625 v 2.5v and below supply voltage relative to gnd, t j =0 ? c to +85 ? cgnd?0.20v cco ? 0.2 v 2.5v and below supply voltage relative to gnd, t j =?40 ? c to +100 ? cgnd?0.20v cco ? 0.2 v i in (4) maximum current through any pin in a powered or unpowered bank when forward biasing the clamp diode. ?10ma v batt (5) battery voltage relative to gnd, t j =0 ? c to +85 ? c1.02.5v battery voltage relative to gnd, t j = ?40 ? c to +100 ? c1.02.5v v fs (6) external voltage supply for efuse programming 2.375 2.625 v notes: 1. configuration data is retained even if v cco drops to 0v. 2. includes v cco of 1.2v, 1.5v, 1.8v, and 2.5v. 3. the configuration supply voltage v cc_config is also known as v cco_0 . 4. a total of 100 ma per bank should not be exceeded. 5. v batt is required only when using bitstream encryption. if battery is not used, connect v batt to either ground or v ccaux . 6. when not programming efuse, connect v fs to gnd. 7. all voltages are relative to ground. ta bl e 1 1 : dc characteristics over recommended operating conditions (1)(2) symbol description min typ max units v drint data retention v ccint voltage (below which configuration data might be lost) 0.75 ? ? v v dri data retention v ccaux voltage (below which configuration data might be lost) 2.0 ? ? v i ref v ref leakage current per pin ? ? 10 a i l input or output leakage current per pin (sample-tested) ? ? 10 a c in (3) die input capacitance at the pad ? ? 8 pf i rpu pad pull-up (when selected) @ v in =0v, v cco = 2.5v 20 ? 80 a pad pull-up (when selected) @ v in =0v, v cco =1.8v 8 ? 40 a pad pull-up (when selected) @ v in =0v, v cco =1.5v 5 ? 30 a pad pull-up (when selected) @ v in =0v, v cco =1.2v 1 ? 20 a i rpd pad pull-down (when selected) @ v in = 2.5v 3 ? 80 a i batt battery supply current ? ? 150 na n temperature diode ideality factor ? 1.0002 ? n r series resistance ?5 ? ? notes: 1. typical values are specified at nominal voltage, 25c. 2. maximum value specified for worst case process at 25c. 3. this measurement represents the die capacitance at the pad, not including the package.
virtex-6 cxt family data sheet ds153 (v1.6) february 11, 2011 www.xilinx.com product specification 13 quiescent supply current: important note typical values for quiescent supply current are specified at nominal voltage, 85c junction temperatures (t j ). xilinx recommends analyzing static power consumption at t j = 85c because the majority of designs operate near the high end of the commercial temperature range. quiescent supply current is specified by speed grade for virtex-6 cxt devices. use the xpower? estimator (xpe) spreadsheet tool (download at http://www.xilinx.com/power ) to calculate static power consumption for conditions other than those specified in ta bl e 1 2 . ta bl e 1 2 : typical quiescent supply current symbol description device speed and temperature grade units -2 (c & i) -1 (c & i) i ccintq quiescent v ccint supply current xc6vcx75t 927 927 ma XC6VCX130T 1563 1563 ma xc6vcx195t 2059 2059 ma xc6vcx240t 2478 2478 ma i ccoq quiescent v cco supply current xc6vcx75t 1 1 ma XC6VCX130T 1 1 ma xc6vcx195t 1 1 ma xc6vcx240t 2 2 ma i ccauxq quiescent v ccaux supply current xc6vcx75t 45 45 ma XC6VCX130T 75 75 ma xc6vcx195t 113 113 ma xc6vcx240t 135 135 ma notes: 1. typical values are specified at nominal voltage, 85c junction temperatures (tj). industrial (i) grade devices have the same typical values as commercial (c) grade devices at 85c, but higher values at 100c. use the xpe tool to calculate 100c values. 2. typical values are for blank configured devices with no output current loads, no active input pull-up resistors, all i/o pins are 3-state and floating. 3. if dci or differential signaling is used, more accurate quiescent current estimates can be obtained by using the xpower estim ator (xpe) or xpower analyzer (xpa) tools.
virtex-6 cxt family data sheet ds153 (v1.6) february 11, 2011 www.xilinx.com product specification 14 power-on power supply requirements xilinx fpgas require a certain amount of su pply current during power-on to insure proper device initialization. the actual current consumed depends on the power-on ramp rate of the power supply. virtex-6 cxt devices require a power-on sequence of v ccint , v ccaux , and v cco . if the requirement can not be met, then v ccaux must always be powered prior to v cco . v ccaux and v cco can be powered by the same supply, therefore, both v ccaux and v cco are permitted to ramp simultaneously. similarly, for the power-down sequence, v cco must be powered down prior to v ccaux or if powered by the same supply, v ccaux and v cco power-down simultaneously. ta bl e 1 3 shows the minimum current, in addition to i ccq , that are required by virtex-6 cxt devices for proper power-on and configuration. if the current minimums shown in ta b l e 1 2 and ta bl e 1 3 are met, the device powers on after all three supplies have passed through their power-on reset threshold voltages. the fpga must be configured after v ccint is applied. once initialized and configured, use the xpower tools to estimate current drain on these supplies. ta bl e 1 3 : power-on current for virtex-6 cxt devices device i ccintmin i ccauxmin i ccomin units typ (1) typ (1) typ (1) xc6vcx75t see i ccintq in ta bl e 1 2 i ccauxq +10 i ccoq + 30 ma per bank ma XC6VCX130T see i ccintq in ta bl e 1 2 i ccauxq +10 i ccoq + 30 ma per bank ma xc6vcx195t see i ccintq in ta bl e 1 2 i ccauxq +40 i ccoq + 30 ma per bank ma xc6vcx240t see i ccintq in ta bl e 1 2 i ccauxq +40 i ccoq + 30 ma per bank ma notes: 1. typical values are specified at nominal voltage, 25c. 2. use the xpower? estimator (xpe) spreadsheet tool (download at http://www.xilinx.com/power ) to calculate maximum power-on currents. ta bl e 1 4 : power supply ramp time symbol description ramp time units v ccint internal supply voltage relative to gnd 0.20 to 50.0 ms v cco output drivers supply voltage relative to gnd 0.20 to 50.0 ms v ccaux auxiliary supply voltage relative to gnd 0.20 to 50.0 ms
virtex-6 cxt family data sheet ds153 (v1.6) february 11, 2011 www.xilinx.com product specification 15 selectio? dc input and output levels values for v il and v ih are recommended input voltages. values for i ol and i oh are guaranteed over the recommended operating conditions at the v ol and v oh test points. only selected standards are tested. these are chosen to ensure that all standards meet their specifications. the selected standards are tested at a minimum v cco with the respective v ol and v oh voltage levels shown. other standards are sample tested. ta bl e 1 5 : selectio dc input and output levels i/o standard v il v ih v ol v oh i ol i oh v, min v, max v, min v, max v, max v, min ma ma lvcmos25, lvdci25 ?0.3 0.7 1.7 v cco +0.3 0.4 v cco ? 0.4 note(3) note(3) lvcmos18, lvdci18 ?0.3 35% v cco 65% v cco v cco + 0.3 0.45 v cco ? 0.45 note(4) note(4) lvcmos15, lvdci15 ?0.3 35% v cco 65% v cco v cco + 0.3 25% v cco 75% v cco note(4) note(4) lvcmos12 ?0.3 35% v cco 65% v cco v cco + 0.3 25% v cco 75% v cco note(5) note(5) hstl i_12 ?0.3 v ref ?0.1 v ref +0.1 v cco + 0.3 25% v cco 75% v cco 6.3 6.3 hstl i (2) ?0.3 v ref ?0.1 v ref +0.1 v cco +0.3 0.4 v cco ?0.4 8 ?8 hstl ii (2) ?0.3 v ref ?0.1 v ref +0.1 v cco +0.3 0.4 v cco ?0.4 16 ?16 hstl iii (2) ?0.3 v ref ?0.1 v ref +0.1 v cco +0.3 0.4 v cco ? 0.4 24 ?8 diff hstl i (2) ?0.3 50% v cco ? 0.1 50% v cco +0.1 v cco +0.3 ? ? ? ? diff hstl ii (2) ?0.3 50% v cco ? 0.1 50% v cco +0.1 v cco +0.3 ? ? ? ? sstl2 i ?0.3 v ref ?0.15 v ref +0.15 v cco +0.3 v tt ?0.61 v tt + 0.61 8.1 ?8.1 sstl2 ii ?0.3 v ref ?0.15 v ref +0.15 v cco +0.3 v tt ?0.81 v tt + 0.81 16.2 ?16.2 diff sstl2 i ?0.3 50% v cco ?0.15 50% v cco +0.15 v cco +0.3 ? ? ? ? diff sstl2 ii ?0.3 50% v cco ?0.15 50% v cco +0.15 v cco +0.3 ? ? ? ? sstl18 i ?0.3 v ref ? 0.125 v ref + 0.125 v cco +0.3 v tt ?0.47 v tt + 0.47 6.7 ?6.7 sstl18 ii ?0.3 v ref ? 0.125 v ref +0.125 v cco +0.3 v tt ?0.60 v tt + 0.60 13.4 ?13.4 diff sstl18 i ?0.3 50% v cco ?0.125 50% v cco +0.125 v cco +0.3 ? ? ? ? diff sstl18 ii ?0.3 50% v cco ?0.125 50% v cco +0.125 v cco +0.3 ? ? ? ? sstl15 ?0.3 v ref ?0.1 v ref +0.1 v cco +0.3 v tt ?0.175 v tt + 0.175 14.3 14.3 notes: 1. tested according to relevant specifications. 2. applies to both 1.5v and 1.8v hstl. 3. using drive strengths of 2, 4, 6, 8, 12, 16, or 24 ma. 4. using drive strengths of 2, 4, 6, 8, 12, or 16 ma. 5. supported drive strengths of 2, 4, 6, or 8 ma. 6. for detailed interface specific dc voltage levels, see the virtex-6 fpga selectio resources user guide .
virtex-6 cxt family data sheet ds153 (v1.6) february 11, 2011 www.xilinx.com product specification 16 ht dc specifications (ht_25) lvds dc specifications (lvds_25) extended lvds dc specif ications (lvdsext_25) ta bl e 1 6 : ht dc specifications symbol dc parameter conditions min typ max units v cco supply voltage 2.38 2.5 2.63 v v od differential output voltage r t = 100 ? across q and q signals 480 600 885 mv ? v od change in v od magnitude ?15 ? 15 mv v ocm output common mode voltage r t = 100 ? across q and q signals 480 600 885 mv ? v ocm change in v ocm magnitude ?15 ? 15 mv v id input differential voltage 200 600 1000 mv ? v id change in v id magnitude ?15 ? 15 mv v icm input common mode voltage 440 600 780 mv ? v icm change in v icm magnitude ?15 ? 15 mv ta bl e 1 7 : lvds dc specifications symbol dc parameter conditions min typ max units v cco supply voltage 2.38 2.5 2.63 v v oh output high voltage for q and q r t = 100 ? across q and q signals ? ? 1.675 v v ol output low voltage for q and q r t = 100 ? across q and q signals 0.825 ? ? v v odiff differential output voltage (q ? q ), q = high (q ?q), q = high r t = 100 ? across q and q signals 247 350 600 mv v ocm output common-mode voltage r t = 100 ? across q and q signals 1.075 1.250 1.425 v v idiff differential input voltage (q ? q ), q = high (q ?q), q = high 100 350 600 mv v icm input common-mode voltage 0.3 1.2 2.2 v ta bl e 1 8 : extended lvds dc specifications symbol dc parameter conditions min typ max units v cco supply voltage 2.38 2.5 2.63 v v oh output high voltage for q and q r t = 100 ? across q and q signals ? ? 1.785 v v ol output low voltage for q and q r t = 100 ? across q and q signals 0.715 ? ? v v odiff differential output voltage (q ? q ), q = high (q ?q), q = high r t = 100 ? across q and q signals 350 ? 840 mv v ocm output common-mode voltage r t = 100 ? across q and q signals 1.075 1.250 1.425 v v idiff differential input voltage (q ? q ), q = high (q ?q), q = high common-mode input voltage = 1.25v 100 ? 1000 mv v icm input common-mode voltage differentia l input voltage = 350 mv 0.3 1.2 2.2 v
virtex-6 cxt family data sheet ds153 (v1.6) february 11, 2011 www.xilinx.com product specification 17 lvpecl dc specifi cations (lvpecl_25) these values are valid when driving a 100 ? differential load only, i.e., a 100 ? resistor between the two receiver pins. the v oh levels are 200 mv below standard lvpecl levels and are co mpatible with devices toler ant of lower common-mode ranges. ta bl e 1 9 summarizes the dc output specif ications of lvpecl. for more information on using lvpecl , see the virtex-6 fpga selectio resources user guide . efuse read endurance ta bl e 2 0 lists the maximum number of read cycle operations expected. for more information, see the virtex-6 fpga configuration user guide . gtx transceiver specifications gtx transceiver dc characteristics ta bl e 1 9 : lvpecl dc specifications symbol dc parameter min typ max units v oh output high voltage v cc ? 1.025 1.545 v cc ?0.88 v v ol output low voltage v cc ? 1.81 0.795 v cc ?1.62 v v icm input common-mode voltage 0.6 ? 2.2 v v idiff differential input voltage (1)(2) 0.100 ? 1.5 v notes: 1. recommended input maximum voltage not to exceed v ccaux +0.2v. 2. recommended input minimum voltage not to go below ?0.5v. ta bl e 2 0 : efuse read endurance symbol description speed grade units -3 -2 -1 -1l dna_cycles number of dna_port read operations or jtag isc_dna read command operations. unaffected by shift operations. 30,000,000 read cycles aes_cycles number of jtag fuse_key or fuse_cntl read command operations. unaffected by shift operations. 30,000,000 read cycles ta bl e 2 1 : absolute maximum ratings for gtx transceivers (1) symbol description min max units mgtavcc analog supply voltage for the gtx transmitter and receiver circuits relative to gnd ?0.5 1.1 v mgtavtt analog supply voltage for the gtx transmitter and receiver termination circuits relative to gnd ?0.5 1.32 v mgtavttrcal analog supply voltage for the resist or calibration circuit of the gtx transceiver column ?0.5 1.32 v v in receiver (rxp/rxn) and transmitter (txp/ txn) absolute input voltage ?0.5 1.32 v v mgtrefclk reference clock absolute input voltage ?0.5 1.32 v notes: 1. stresses beyond those listed under absolute maximum ratings might cause permanent damage to the device. these are stress rati ngs only, and functional operation of the device at these or any other conditions beyond those listed under operating conditions is not implied. exposure to absolute maximum ratings conditions for extended periods of time might affect device reliability.
virtex-6 cxt family data sheet ds153 (v1.6) february 11, 2011 www.xilinx.com product specification 18 ta bl e 2 2 : recommended operating conditions for gtx transceivers (1)(2) symbol description min typ max units mgtavcc analog supply voltage for the gtx transmitter and receiver circuits relative to gnd 0.95 1.0 1.06 v mgtavtt analog supply voltage for the gtx transmitter and receiver termination circuits relative to gnd 1.14 1.2 1.26 v mgtavttrcal analog supply voltage for the resist or calibration circuit of the gtx transceiver column 1.14 1.2 1.26 v notes: 1. each voltage listed requires the filter circuit described in virtex-6 fpga gtx transceivers user guide . 2. voltages are specified for the temperature range of t j = ?40c to +100c. ta bl e 2 3 : gtx transceiver supply current (per lane) (1)(2) symbol description typ max units i mgtavtt mgtavtt supply current for one gtx transceiver 55.9 note 2 ma i mgtavcc mgtavcc supply current for one gtx transceiver 56.1 ma mgtr ref precision reference resistor for internal calibration termination 100.0 1% tolerance ? notes: 1. typical values are specified at nominal voltage, 25c, with a 3.125 gb/s line rate. 2. values for currents other than the values specified in this table can be obtained by using the xpower estimator (xpe) or xpow er analyzer (xpa) tools. ta bl e 2 4 : gtx transceiver quiescent supply current (per lane) (1)(2)(3) symbol description typ (4) max units i mgtavttq quiescent mgtavtt supply curre nt for one gtx transceiver 0.9 note 2 ma i mgtavccq quiescent mgtavcc supply current for one gtx transceiver 3.5 ma notes: 1. device powered and unconfigured. 2. currents for conditions other than values specified in this tabl e can be obtained by using the xpower estimator (xpe) or xpow er analyzer (xpa) tools. 3. gtx transceiver quiescent supply current for an entire device can be calculated by multiplying the values in this table by th e number of available gtx transceivers. 4. typical values are specified at nominal voltage, 25c.
virtex-6 cxt family data sheet ds153 (v1.6) february 11, 2011 www.xilinx.com product specification 19 gtx transceiver dc input and output levels ta bl e 2 5 summarizes the dc output specifications of the gt x transceivers in virtex-6 cxt fpgas. consult the virtex-6 fpga gtx transceivers user guide for further details. ta bl e 2 5 : gtx transceiver dc specifications symbol dc parameter conditions min typ max units dv ppin differential peak-to-peak input voltage external ac coupled 125 ? 2000 mv v in absolute input voltage dc coupled mgtavtt = 1.2v ?400 ? mgtavtt mv v cmin common mode input voltage dc coupled mgtavtt = 1.2v ? 2/3 mgtavtt ? mv dv ppout differential peak-to-peak output voltage (1) transmitter output swing is set to maximum setting ? ? 1000 mv v cmoutdc dc common mode output voltage equation based mgtavtt ? dv ppout /4 mv r in differential input resistance 80 100 130 ? r out differential output resistance 80 100 120 ? t oskew transmitter output pair (txp and txn) intra-pair skew ? 2 8 ps c ext recommended external ac coupling capacitor (2) ? 100 ? nf notes: 1. the output swing and preemphasis levels are programmable using the attributes discussed in virtex-6 fpga gtx transceivers user guide and can result in values lower than reported in this table. 2. other values can be used as appropriate to conform to specific protocols and standards. x-ref target - figure 11 figure 11: single-ended peak-to-peak voltage x-ref target - figure 12 figure 12: differential peak-to-peak voltage 0 +v p n d s 15 3 _11_041410 s ingle-ended volt a ge 0 +v ?v p?n d s 15 3 _12_041410 differenti a l volt a ge
virtex-6 cxt family data sheet ds153 (v1.6) february 11, 2011 www.xilinx.com product specification 20 ta bl e 2 6 summarizes the dc specifications of the clock input of the gtx transceiver. consult the virtex-6 fpga gtx transceivers user guide for further details. gtx transceiver switching characteristics consult virtex-6 fpga gtx transceivers user guide for further information. ta bl e 2 6 : gtx transceiver clock dc input level specification symbol dc parameter conditions min typ max units v idiff differential peak-to-peak input voltage 210 800 2000 mv r in differential input resistance 90 100 130 ? c ext required external ac coupling capacitor ? 100 ? nf ta bl e 2 7 : gtx transceiver performance symbol description speed grade units -2 -1 f gtxmax maximum gtx transceiver data rate 3.75 3.75 gb/s f gpllmax maximum pll frequency 2.5 2.5 ghz f gpllmin minimum pll frequency 1.2 1.2 ghz ta bl e 2 8 : gtx transceiver dynamic reconfiguration port (drp) switching characteristics symbol description speed grade units -2 -1 f gtxdrpclk gtxdrpclk maximum frequency 100 100 mhz ta bl e 2 9 : gtx transceiver reference clock switching characteristics symbol description conditions all speed grades units min typ max f gclk reference clock frequency range 67.5 ? 375 mhz t rclk reference clock rise time 20% ? 80% ? 200 ? ps t fclk reference clock fall time 80% ? 20% ? 200 ? ps t dcref reference clock duty cycle transceiver pll only 45 50 55 % t lock clock recovery frequency acquisition time initial pll lock ? ? 1 ms t phase clock recovery phase acquisition time lock to data after pll has locked to the reference clock ? ? 200 s x-ref target - figure 13 figure 13: reference clock timing parameters d s 15 3 _1 3 _041410 8 0 % 20 % t fclk t rclk
virtex-6 cxt family data sheet ds153 (v1.6) february 11, 2011 www.xilinx.com product specification 21 ta bl e 3 0 : gtx transceiver user clock switching characteristics (1) symbol description conditions speed grade units -2 -1 f txout txoutclk maximum frequency internal 20-bit data path 187.5 187.5 mhz internal 16-bit data path 234.38 234.38 mhz f rxrec rxrecclk maximum frequency internal 20-bit data path 187.5 187.5 mhz internal 16-bit data path 234.38 234.38 mhz t rx rxusrclk maximum frequency 234.38 234.38 mhz t rx2 rxusrclk2 maximum frequency 1 byte interface 376 312.5 mhz 2 byte interface 234.38 234.38 mhz 4 byte interface 117.19 117.19 mhz t tx txusrclk maximum frequency 234.38 234.38 mhz t tx2 txusrclk2 maximum frequency 1 byte interface 376 312.5 mhz 2 byte interface 234.38 234.38 mhz 4 byte interface 117.19 117.19 mhz notes: 1. clocking must be implemented as described in virtex-6 fpga gtx transceivers user guide . ta bl e 3 1 : gtx transceiver transmitter switching characteristics symbol description condition min typ max units f gtxtx serial data rate range 0.480 ? f gtxmax gb/s t rtx tx rise time 20%?80% ? 120 ? ps t ftx tx fall time 80%?20% ? 120 ? ps t llskew tx lane-to-lane skew (1) ? ? 350 ps v txoobvdpp electrical idle amplitude ? ? 15 mv t txoobtransition electrical idle transition time ? ? 75 ns t j3.75 total jitter (2)(3) 3.75 gb/s ? ? 0.34 ui d j3.75 deterministic jitter (2)(3) ? ? 0.16 ui t j3.125 total jitter (2)(3) 3.125 gb/s ? ? 0.2 ui d j3.125 deterministic jitter (2)(3) ??0.1ui t j3.125l total jitter (2)(3) 3.125 gb/s (4) ? ? 0.35 ui d j3.125l deterministic jitter (2)(3) ? ? 0.16 ui t j2.5 total jitter (2)(3) 2.5 gb/s (5) ? ? 0.20 ui d j2.5 deterministic jitter (2)(3) ? ? 0.08 ui t j1.25 total jitter (2)(3) 1.25 gb/s (6) ? ? 0.15 ui d j1.25 deterministic jitter (2)(3) ? ? 0.06 ui t j600 total jitter (2)(3) 600 mb/s ? ? 0.1 ui d j600 deterministic jitter (2)(3) ? ? 0.03 ui
virtex-6 cxt family data sheet ds153 (v1.6) february 11, 2011 www.xilinx.com product specification 22 t j480 total jitter (2)(3) 480 mb/s ? ? 0.1 ui d j480 deterministic jitter (2)(3) ? ? 0.03 ui notes: 1. using same refclk input with txenpmaphasealign enab led for up to four consecutive gtx transceiver sites. 2. using pll_divsel_fb = 2, 20-bit internal data width. these values are not intended for protocol specific compliance determinati ons. 3. all jitter values are based on a bit-error ratio of 1e -12 . 4. pll frequency at 1.5625 ghz and outdiv = 1. 5. pll frequency at 2.5 ghz and outdiv = 2. 6. pll frequency at 2.5 ghz and outdiv = 4. ta bl e 3 2 : gtx transceiver receiver switching characteristics symbol description min typ max units f gtxrx serial data rate rx oversampler not enabled 0.600 ? f gtxmax gb/s rx oversampler enabled 0.480 ? 0.600 gb/s t rxelecidle time for rxelecidle to respond to loss or restoration of data ? 75 ? ns r xoobvdpp oob detect threshold peak-to-peak 60 ? 150 mv r xsst receiver spread-spectrum tracking (1) modulated @ 33 khz ?5000 ? 0 ppm r xrl run length (cid) internal ac capacitor bypassed ? ? 512 ui r xppmtol data/refclk ppm offset tolerance cdr 2 nd -order loop disabled ?200 ? 200 ppm cdr 2 nd -order loop enabled ?2000 ? 2000 ppm sj jitter tolerance (2) jt_sj 3.75 sinusoidal jitter (3) 3.75 gb/s 0.44 ? ? ui jt_sj 3.125 sinusoidal jitter (3) 3.125 gb/s 0.45 ? ? ui jt_sj 3.125l sinusoidal jitter (3) 3.125 gb/s (4) 0.45 ? ? ui jt_sj 2.5 sinusoidal jitter (3) 2.5 gb/s (5) 0.5 ? ? ui jt_sj 1.25 sinusoidal jitter (3) 1.25 gb/s (6) 0.5 ? ? ui jt_sj 675 sinusoidal jitter (3) 675 mb/s 0.4 ? ? ui jt_sj 480 sinusoidal jitter (3) 480 mb/s 0.4 ? ? ui sj jitter tolerance with stressed eye (2) jt_tjse 3.125 total jitter wi th stressed eye (7) 3.125 gb/s 0.70 ? ? ui jt_sjse 3.125 sinusoidal jitter with stressed eye (7) 3.125 gb/s 0.1 ? ? ui notes: 1. using pll_rxdivsel_out = 1, 2, and 4. 2. all jitter values are based on a bit-error ratio of 1e ?12 . 3. the frequency of the injected sinusoidal jitter is 80 mhz. 4. pll frequency at 1.5625 ghz and outdiv = 1. 5. pll frequency at 2.5 ghz and outdiv = 2. 6. pll frequency at 2.5 ghz and outdiv = 4. 7. composite jitter with rx equalizer enabled. dfe disabled. ta bl e 3 1 : gtx transceiver transmitter switching characteristics (cont?d) symbol description condition min typ max units
virtex-6 cxt family data sheet ds153 (v1.6) february 11, 2011 www.xilinx.com product specification 23 ethernet mac switching characteristics consult virtex-6 fpga embedded tri-mode ethernet mac user guide for further information. integrated interface block for pci ex press designs switching characteristics more information and documentation on soluti ons for pci express designs can be found at: http://www.xilinx.com /technology/protoco ls/pciexpress.htm ta bl e 3 3 : maximum ethernet mac performance symbol description conditions speed grade units -2 -1 f temacclient client interface maximum frequency 10 mb/s ? 8-bit width 2.5 (1) 2.5 (1) mhz 100 mb/s ? 8-bit width 25 (2) 25 (2) mhz 1000 mb/s ? 8-bit width 125 125 mhz 1000 mb/s ? 16-bit width 62.5 62.5 mhz f temacphy physical interface maximum frequency 10 mb/s ? 4-bit width 2.5 2.5 mhz 100 mb/s ? 4-bit width 25 25 mhz 1000 mb/s ? 8-bit width 125 125 mhz notes: 1. when not using clock enable, the f max is lowered to 1.25 mhz. 2. when not using clock enable, the f max is lowered to 12.5 mhz. ta bl e 3 4 : maximum performance for pci express designs symbol description speed grade units -2 -1 f pipeclk pipe clock maximum frequency 125 125 mhz f userclk user clock maximum frequency 250 250 mhz f drpclk drp clock maximum frequency 250 250 mhz
virtex-6 cxt family data sheet ds153 (v1.6) february 11, 2011 www.xilinx.com product specification 24 performance characteristics this section provides the performance characteristics of some common functions and designs implemented in virtex-6 cxt devices. the numbers reported here are worst-case values; they have all been fully characterized. these values are subject to the same guidelines as the switching characteristics, page 25 . ta bl e 3 5 : interface performances description speed grade -2 -1 networking applications sdr lvds transmitter (using oserdes; data_width = 4 to 8) 650 mb/s 625 mb/s ddr lvds transmitter (using oserdes; data_width = 4 to 10) 1.25 gb/s 1.0 gb/s sdr lvds receiver (sfi-4.1) (1) 650 mb/s 625 mb/s ddr lvds receiver (sfi-4.2) (1) 1.0 gb/s 0.9 gb/s maximum physical interface (phy) rate for memory interfaces (2)(3) ddr2 666 mb/s 666 mb/s ddr3 800 mb/s 666 mb/s qdr ii + sram 250 mhz 250 mhz notes: 1. lvds receivers are typically bounded with certain applications where specific dpa algorithms dominate deterministic performan ce. 2. based on xilinx memory characterization platforms designed according to the guidelines in the virtex-6 fpga memory interface solutions user guide . 3. consult the virtex-6 fpga memory interface solutions data sheet for performance and feature information on memory interface cores (controller plus phy).
virtex-6 cxt family data sheet ds153 (v1.6) february 11, 2011 www.xilinx.com product specification 25 switching characteristics all values represented in this data sheet are based on the speed specification (version 1.08). switching characteristics are specified on a per-speed-grade basis and can be designated as advance, preliminary, or production. each designation is defined as follows: advance these specifications are based on simulations only and are typically available soon after device design specifications are frozen. although speed grades with this designation are considered relatively stable and conservative, some under- reporting might still occur. preliminary these specifications are based on complete es (engineering sample) silicon characterization. devices and speed grades with this designation are intended to give a better indication of the expected performance of production silicon. the probability of under -reporting delays is greatly reduced as compared to advance data. production these specifications are released once enough production silicon of a particular devi ce family member has been characterized to provide full correlation between specifications and devices over numerous production lots. there is no under-reporting of delays, and customers receive formal notification of any subsequent changes. typically, the slowest speed grades transition to production before faster speed grades. all specifications are always representative of worst-case supply voltage and junction temperature conditions. since individual family members are produced at different times, the migration from one category to another depends completely on the status of the fabrication process for each device. ta b l e 3 6 correlates the current status of each virtex-6 cxt device on a per speed grade basis. testing of switching characteristics all devices are 100% functionally tested. internal timing parameters are derived from measuring internal test patterns. listed below are representative values. for more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer and back-annotate to the simulation net list. unless otherwise noted, values apply to all virtex-6 cxt devices. production silicon and ise software status in some cases, a particular family member (and speed grade) is released to production before a speed specification is released with the correct label (advance, preliminary, production). any labeling discrepancies are corrected in subsequent speed specification releases. ta bl e 3 7 lists the production released virtex-6 family member, speed grade, and the minimum corresponding supported speed specification version and ise software revisions. the ise? software and speed specifications listed are the minimum releases required for production. all subsequent releases of software and speed specifications are valid. ta b l e 3 6 : virtex-6 cxt device/speed grade designations device speed grade designations advance preliminary production xc6vcx75t -2, -1 XC6VCX130T -2, -1 xc6vcx195t -2, -1 xc6vcx240t -2, -1 ta b l e 3 7 : virtex-6 cxt device/production software and speed specification release device speed grade designations -2 -1 xc6vcx75t ise 12.2 (with speed file patch) v1.06 XC6VCX130T ise 12.1 v1.04 xc6vcx195t ise 12.2 (with speed file patch) v1.06 xc6vcx240t ise 12.1 v1.04 notes: 1. blank entries indicate a device and/or speed grade in advance or preliminary status.
virtex-6 cxt family data sheet ds153 (v1.6) february 11, 2011 www.xilinx.com product specification 26 iob pad input/output/3-state switching characteristics ta bl e 3 8 summarizes the values of standard-specific data input delay adjustments, output delays terminating at pads (based on standard) and 3-state delays. t iopi is described as the delay from iob pad through the input buffer to the i-pin of an iob pad. the delay varies depending on th e capability of the selectio input buffer. t ioop is described as the delay from the o pin to the iob pad through the output buffer of an iob pad. the delay varies depending on the capability of th e selectio output buffer. t iotp is described as the delay from the t pin to the iob pad through the output buffer of an iob pad, when 3-state is disabled. the delay varies depending on the selectio capability of the output buffer. ta b l e 3 9 summarizes the value of t iotphz . t iotphz is described as the delay from the t pin to the iob pad through the output buffer of an iob pad, when 3-state is enabled (i.e., a high impedance state). ta bl e 3 8 : iob switching characteristics i/o standard t iopi t ioop t iotp units speed grade speed grade speed grade -2 -1 -2 -1 -2 -1 lvds_25 1.09 1.09 1. 68 1.68 1.68 1.68 ns lvdsext_25 1.09 1.09 1 .84 1.84 1.84 1.84 ns ht_25 1.09 1.09 1.78 1.78 1.78 1.78 ns blvds_25 1.09 1.09 1. 67 1.67 1.67 1.67 ns rsds_25 (point to point) 1 .09 1.09 1.68 1.68 1.68 1.68 ns hstl_i 1.06 1.06 1. 73 1.73 1.73 1.73 ns hstl_ii 1.06 1.06 1.74 1.74 1.74 1.74 ns hstl_iii 1.06 1.06 1. 71 1.71 1.71 1.71 ns hstl_i_18 1.06 1.06 1. 75 1.75 1.75 1.75 ns hstl_ii_18 1.06 1.06 1.81 1.81 1.81 1.81 ns hstl_iii_18 1.06 1.06 1.71 1.71 1.71 1.71 ns sstl2_i 1.06 1.06 1. 77 1.77 1.77 1.77 ns sstl2_ii 1.06 1.06 1.72 1.72 1.72 1.72 ns sstl15 1.06 1.06 1.71 1.71 1.71 1.71 ns lvcmos25, slow, 2 ma 0.66 0 .66 6.01 6.01 6.01 6.01 ns lvcmos25, slow, 4 ma 0.66 0 .66 3.79 3.79 3.79 3.79 ns lvcmos25, slow, 6 ma 0.66 0 .66 3.08 3.08 3.08 3.08 ns lvcmos25, slow, 8 ma 0.66 0 .66 2.72 2.72 2.72 2.72 ns lvcmos25, slow, 12 ma 0.66 0.66 2.17 2.17 2.17 2.17 ns lvcmos25, slow, 16 ma 0.66 0.66 2.29 2.29 2.29 2.29 ns lvcmos25, slow, 24 ma 0.66 0.66 2.02 2.02 2.02 2.02 ns lvcmos25, fast, 2 ma 0.66 0.66 6.04 6.04 6.04 6.04 ns lvcmos25, fast, 4 ma 0.66 0.66 3.82 3.82 3.82 3.82 ns lvcmos25, fast, 6 ma 0.66 0.66 2.99 2.99 2.99 2.99 ns lvcmos25, fast, 8 ma 0.66 0.66 2.65 2.65 2.65 2.65 ns lvcmos25, fast, 12 ma 0.66 0.66 2.08 2.08 2.08 2.08 ns lvcmos25, fast, 16 ma 0.66 0.66 2.13 2.13 2.13 2.13 ns lvcmos25, fast, 24 ma 0.66 0.66 1.99 1.99 1.99 1.99 ns
virtex-6 cxt family data sheet ds153 (v1.6) february 11, 2011 www.xilinx.com product specification 27 lvcmos18, slow, 2 ma 0.71 0 .71 4.87 4.87 4.87 4.87 ns lvcmos18, slow, 4 ma 0.71 0 .71 3.21 3.21 3.21 3.21 ns lvcmos18, slow, 6 ma 0.71 0 .71 2.64 2.64 2.64 2.64 ns lvcmos18, slow, 8 ma 0.71 0 .71 2.27 2.27 2.27 2.27 ns lvcmos18, slow, 12 ma 0.71 0.71 2.15 2.15 2.15 2.15 ns lvcmos18, slow, 16 ma 0.71 0.71 2.11 2.11 2.11 2.11 ns lvcmos18, fast, 2 ma 0.71 0.71 4.57 4.57 4.57 4.57 ns lvcmos18, fast, 4 ma 0.71 0.71 2.97 2.97 2.97 2.97 ns lvcmos18, fast, 6 ma 0.71 0.71 2.46 2.46 2.46 2.46 ns lvcmos18, fast, 8 ma 0.71 0.71 2.13 2.13 2.13 2.13 ns lvcmos18, fast, 12 ma 0.71 0.71 1.97 1.97 1.97 1.97 ns lvcmos18, fast, 16 ma 0.71 0.71 1.91 1.91 1.91 1.91 ns lvcmos15, slow, 2 ma 0.85 0 .85 4.29 4.29 4.29 4.29 ns lvcmos15, slow, 4 ma 0.85 0 .85 3.10 3.10 3.10 3.10 ns lvcmos15, slow, 6 ma 0.85 0 .85 2.68 2.68 2.68 2.68 ns lvcmos15, slow, 8 ma 0.85 0 .85 2.23 2.23 2.23 2.23 ns lvcmos15, slow, 12 ma 0.85 0.85 2.13 2.13 2.13 2.13 ns lvcmos15, slow, 16 ma 0.85 0.85 2.04 2.04 2.04 2.04 ns lvcmos15, fast, 2 ma 0.85 0.85 4.28 4.28 4.28 4.28 ns lvcmos15, fast, 4 ma 0.85 0.85 2.78 2.78 2.78 2.78 ns lvcmos15, fast, 6 ma 0.85 0.85 2.42 2.42 2.42 2.42 ns lvcmos15, fast, 8 ma 0.85 0.85 2.11 2.11 2.11 2.11 ns lvcmos15, fast, 12 ma 0.85 0.85 1.97 1.97 1.97 1.97 ns lvcmos15, fast, 16 ma 0.85 0.85 1.96 1.96 1.96 1.96 ns lvcmos12, slow, 2 ma 0.93 0 .93 3.75 3.75 3.75 3.75 ns lvcmos12, slow, 4 ma 0.93 0 .93 2.93 2.93 2.93 2.93 ns lvcmos12, slow, 6 ma 0.93 0 .93 2.41 2.41 2.41 2.41 ns lvcmos12, slow, 8 ma 0.93 0 .93 2.25 2.25 2.25 2.25 ns lvcmos12, fast, 2 ma 0.93 0.93 3.39 3.39 3.39 3.39 ns lvcmos12, fast, 4 ma 0.93 0.93 2.51 2.51 2.51 2.51 ns lvcmos12, fast, 6 ma 0.93 0.93 2.11 2.11 2.11 2.11 ns lvcmos12, fast, 8 ma 0.93 0.93 2.02 2.02 2.02 2.02 ns lvdci_25 0.66 0.66 2. 26 2.26 2.26 2.26 ns lvdci_18 0.71 0.71 2. 47 2.47 2.47 2.47 ns lvdci_15 0.85 0.85 2. 24 2.24 2.24 2.24 ns lvdci_dv2_25 0.66 0.66 2.01 2.01 2.01 2.01 ns lvdci_dv2_18 0.71 0.71 2.00 2.00 2.00 2.00 ns lvdci_dv2_15 0.85 0.85 1.91 1.91 1.91 1.91 ns ta bl e 3 8 : iob switching characteristics (cont?d) i/o standard t iopi t ioop t iotp units speed grade speed grade speed grade -2 -1 -2 -1 -2 -1
virtex-6 cxt family data sheet ds153 (v1.6) february 11, 2011 www.xilinx.com product specification 28 lvpecl_25 1.09 1.09 1.65 1.65 1.65 1.65 ns hstl_i_12 1.06 1.06 1. 78 1.78 1.78 1.78 ns hstl_i_dci 1.06 1.06 1.66 1.66 1.66 1.66 ns hstl_ii_dci 1.06 1.06 1.68 1.68 1.68 1.68 ns hstl_ii_t_dci 1.06 1.06 1.66 1.66 1.66 1.66 ns hstl_iii_dci 1.06 1.06 1.62 1.62 1.62 1.62 ns hstl_i_dci_18 1.06 1.06 1.68 1.68 1.68 1.68 ns hstl_ii_dci_18 1.06 1.06 1.62 1.62 1.62 1.62 ns hstl_ii _t_dci_18 1.06 1 .06 1.68 1.68 1.68 1.68 ns hstl_iii_dci_18 1.06 1.0 61.691.691.691.69 ns diff_hstl_i_18 1.09 1.09 1.75 1.75 1.75 1.75 ns diff_hstl_i_dci_18 1.09 1 .09 1.68 1.68 1.68 1.68 ns diff_hstl_i 1.09 1.09 1.73 1.73 1.73 1.73 ns diff_hstl_i_dci 1.09 1. 09 1.66 1.66 1.66 1.66 ns diff_hstl_ii_18 1.09 1. 09 1.81 1.81 1.81 1.81 ns diff_hstl_ii_dci_18 1.09 1.09 1.62 1.62 1.62 1.62 ns diff_hstl_ii _t_dci_18 1.0 91.091.681.681.681.68 ns diff_hstl_ii 1.09 1.09 1.74 1.74 1.74 1.74 ns diff_hstl_ii_dci 1.09 1. 09 1.68 1.68 1.68 1.68 ns sstl2_i_dci 1.06 1.06 1.70 1.70 1.70 1.70 ns sstl2_ii_dci 1.06 1.06 1.67 1.67 1.67 1.67 ns sstl2_ii_t_dci 1.06 1.06 1.70 1.70 1.70 1.70 ns sstl18_i 1.06 1.06 1.75 1.75 1.75 1.75 ns sstl18_ii 1.06 1.06 1. 67 1.67 1.67 1.67 ns sstl18_i_dci 1.06 1.06 1.67 1.67 1.67 1.67 ns sstl18_ii_dci 1.06 1.06 1.63 1.63 1.63 1.63 ns sstl18_ii_t_dci 1.06 1. 06 1.67 1.67 1.67 1.67 ns sstl15_t_dci 1.06 1.06 1.68 1.68 1.68 1.68 ns sstl15_dci 1.06 1.06 1. 68 1.68 1.68 1.68 ns diff_sstl2_i 1.09 1.09 1.77 1.77 1.77 1.77 ns diff_sstl2_i_dci 1.09 1. 09 1.70 1.70 1.70 1.70 ns diff_sstl2_ii 1.09 1.09 1.72 1.72 1.72 1.72 ns diff_sstl2_ii_dci 1.09 1. 09 1.67 1.67 1.67 1.67 ns diff_sstl2_ii_t_dci 1.09 1. 09 1.70 1.70 1.70 1.70 ns diff_sstl18_i 1.09 1.09 1.75 1.75 1.75 1.75 ns diff_sstl18_i_dci 1.09 1. 09 1.67 1.67 1.67 1.67 ns diff_sstl18_ii 1.09 1.09 1.67 1.67 1.67 1.67 ns diff_sstl18_ii_dci 1.09 1. 09 1.63 1.63 1.63 1.63 ns ta bl e 3 8 : iob switching characteristics (cont?d) i/o standard t iopi t ioop t iotp units speed grade speed grade speed grade -2 -1 -2 -1 -2 -1
virtex-6 cxt family data sheet ds153 (v1.6) february 11, 2011 www.xilinx.com product specification 29 i/o standard adjustment measurement methodology input delay measurements ta bl e 4 0 shows the test setup parameters used for measuring input delay. diff_sstl18_ii_t_ dci 1.09 1.09 1.67 1.67 1.67 1.67 ns diff_sstl15 1.06 1.06 1.71 1.71 1.71 1.71 ns diff_sstl15_dci 1.06 1.06 1.68 1.68 1.68 1.68 ns diff_sstl15_t_dci 1.06 1. 06 1.68 1.68 1.68 1.68 ns ta bl e 3 9 : iob 3-state on output switching characteristics (t iotphz ) symbol description speed grade units -2 -1 t iotphz t input to pad high-impedance 0.99 0.99 ns ta bl e 3 8 : iob switching characteristics (cont?d) i/o standard t iopi t ioop t iotp units speed grade speed grade speed grade -2 -1 -2 -1 -2 -1 ta bl e 4 0 : input delay measurement methodology description i /o standard attribute v l (1)(2) v h (1)(2) v meas (1,4,5) v ref (1,3,5) lvcmos, 2.5v lvcmos25 0 2.5 1.25 ? lvcmos, 1.8v lvcmos18 0 1.8 0.9 ? lvcmos, 1.5v lvcmos15 0 1.5 0.75 ? hstl (high-speed transceiver logic), class i & ii hstl_i, hstl_ii v ref ?0.5 v ref +0.5 v ref 0.75 hstl, class iii hstl_iii v ref ?0.5 v ref +0.5 v ref 0.90 hstl, class i & ii, 1.8v hstl_i_18, hstl_ii_18 v ref ?0.5 v ref +0.5 v ref 0.90 hstl, class iii 1.8v hstl_iii_18 v ref ?0.5 v ref +0.5 v ref 1.08 sstl (stub terminated transceiver logic), class i & ii, 3.3v sstl3_i, sstl3_ii v ref ?1.00 v ref +1.00 v ref 1.5 sstl, class i & ii, 2. 5v sstl2_i, sstl2_ii v ref ?0.75 v ref +0.75 v ref 1.25 sstl, class i & ii, 1.8v sstl18_i, sstl18_ii v ref ?0.5 v ref +0.5 v ref 0.90 lvds (low-voltage differential signal ing), 2.5v lvds_25 1.2 ? 0.125 1.2 + 0.125 0 (6) ? lvdsext (lvds extended mode), 2. 5v lvdsext_25 1.2 ? 0.125 1.2 + 0.125 0 (6) ? ht (hypertransport), 2.5v ldt_25 0.6 ? 0.125 0.6 + 0.125 0 (6) ? notes: 1. the input delay measurement methodology parameters for lvdci are the same for lvcmos standards of the same voltage. input del ay measurement methodology parameters for hslvdci are the same as for hstl_ii standards of the same voltage. parameters for all ot her dci standards are the same for the corresponding non-dci standards. 2. input waveform switches between v l and v h . 3. measurements are made at typical, minimum, and maximum v ref values. reported delays reflect worst case of these measurements. v ref values listed are typical. 4. input voltage level from which measurement starts. 5. this is an input voltage reference that bears no relation to the v ref / v meas parameters found in ibis models and/or noted in figure 14 . 6. the value given is the differential output voltage.
virtex-6 cxt family data sheet ds153 (v1.6) february 11, 2011 www.xilinx.com product specification 30 output delay measurements output delays are measured using a tektronix p6245 tds500/600 probe (< 1 pf) across approximately 4" of fr4 microstrip trace. standard termination was used for all testing. the propagation delay of the 4" trace is characterized separately and subtracted from the final measurement, and is therefore not included in the generalized test setups shown in figure 14 and figure 15 . measurements and test conditions are reflected in the ibis models except where the ibis format precludes it. parameters v ref , r ref , c ref , and v meas fully describe the test conditions for each i/o standard. the most accurate prediction of propagation delay in any given application can be obtained through ibis simulation, using the following method: 1. simulate the output driver of choice into the generalized test setup, using values from ta b l e 4 1 . 2. record the time to v meas . 3. simulate the output driver of choice into the actual pcb trace and load, using the appropriate ibis model or capacitance value to represent the load. 4. record the time to v meas . 5. compare the results of steps 2 and 4. the increase or decrease in delay yields the actual propagation delay of the pcb trace. x-ref target - figure 14 figure 14: single ended test setup v ref r ref v mea s (volt a ge level when t a king del a y me asu rement) c ref (pro b e c a p a cit a nce) fpga o u tp u t d s 152_06_042109 x-ref target - figure 15 figure 15: differential test setup r ref v mea s + ? c ref fpga o u tp u t d s 152_07_042109 ta bl e 4 1 : output delay measurement methodology description i/o standard attribute r ref ( ? ) c ref (1) (pf) v meas (v) v ref (v) lvcmos, 2.5v lvcmos25 1m 0 1.25 0 lvcmos, 1.8v lvcmos18 1m 0 0.9 0 lvcmos, 1.5v lvcmos15 1m 0 0.75 0 lvcmos, 1.2v lvcmos12 1m 0 0.75 0 hstl (high-speed transceiver logic), class i hstl_i 50 0 v ref 0.75 hstl, class ii hstl_ii 25 0 v ref 0.75 hstl, class iii hstl_iii 50 0 0.9 1.5 hstl, class i, 1.8v hstl_i_18 50 0 v ref 0.9 hstl, class ii, 1.8v hstl_ii_18 25 0 v ref 0.9 hstl, class iii, 1.8v hstl_iii_18 50 0 1.1 1.8 sstl (stub series terminated logic), class i, 1.8v sstl18_i 50 0 v ref 0.9 sstl, class ii, 1.8v sstl18_ii 25 0 v ref 0.9 sstl, class i, 2.5v sstl2_i 50 0 v ref 1.25 sstl, class ii, 2.5v sstl2_ii 25 0 v ref 1.25 lvds (low-voltage differential signaling), 2.5v lvds_25 100 0 0 (2) 1.2 lvdsext (lvds extended mode), 2.5v lvds_25 100 0 0 (2) 1.2 blvds (bus lvds), 2.5v blvds_25 100 0 0 (2) 0
virtex-6 cxt family data sheet ds153 (v1.6) february 11, 2011 www.xilinx.com product specification 31 input/output logic switching characteristics ht (hypertransport), 2.5v ldt_25 100 0 0 (2) 0.6 lvpecl (low-voltage positi ve emitter-coupled logic), 2.5v lvpecl_25 100 0 0 (2) 0 lvdci/hslvdci, 2.5v lvdci_25, hslvdci_25 1m 0 1.25 0 lvdci/hslvdci, 1.8v lvdci_18, hslvdci_18 1m 0 0.9 0 lvdci/hslvdci, 1.5v lvdci_15, hslvdci_15 1m 0 0.75 0 hstl (high-speed transceiver logic), class i & ii, with dci hstl_i_dci, hstl_ii_dci 50 0 v ref 0.75 hstl, class iii, with dci hstl_iii_dci 50 0 0.9 1.5 hstl, class i & ii, 1.8v, with dci hstl_i_dci_18, hstl_ii_dci_18 50 0 v ref 0.9 hstl, class iii, 1.8v, with dci hstl_iii_dci_18 50 0 1.1 1.8 sstl (stub series termi.logic), class i & ii, 1.8v, with dci sstl18_i_dci, sstl18_ii_dci 50 0 v ref 0.9 sstl, class i & ii, 2.5v, with dci sstl2_i_dci, sstl2_ii_dci 50 0 v ref 1.25 notes: 1. c ref is the capacitance of the probe, nominally 0 pf. 2. the value given is the differential output voltage. ta bl e 4 2 : ilogic switching characteristics symbol description speed grade units -2 -1 setup/hold t ice1ck /t ickce1 ce1 pin setup/hold with respec t to clk 0.27/0.04 0.27/0.04 ns t isrck /t icksr sr pin setup/hold with respect to clk 0.96/?0.10 0.96/?0.10 ns t idock /t iockd d pin setup/hold with respect to clk without delay 0.10/0.54 0.10/0.54 ns t idockd /t iockdd ddly pin setup/hold with respect to cl k (using iodelay) 0.14/0.42 0.14/0.40 ns combinatorial t idi d pin to o pin propagation delay, no delay 0.20 0.20 ns t idid ddly pin to o pin propagation delay (using iodelay) 0.25 0.25 ns sequential delays t idlo d pin to q1 pin using flip-flop as a latch without delay 0.64 0.64 ns t idlod ddly pin to q1 pin using flip-flop as a latch (using iodelay) 0.68 0.68 ns t ickq clk to q outputs 0.71 0.71 ns t rq_ilogic sr pin to oq/tq out 1.15 1.15 ns t gsrq_ilogic global set/reset to q outputs 10.51 10.51 ns set/reset t rpw_ilogic minimum pulse width, sr inputs 1.20 1.20 ns, min ta bl e 4 1 : output delay measurement methodology (cont?d) description i/o standard attribute r ref ( ? ) c ref (1) (pf) v meas (v) v ref (v)
virtex-6 cxt family data sheet ds153 (v1.6) february 11, 2011 www.xilinx.com product specification 32 input serializer/deserializer switching characteristics ta bl e 4 3 : ologic switching characteristics symbol description speed grade units -2 -1 setup/hold t odck /t ockd d1/d2 pins setup/hold with res pect to clk 0.54/?0.11 0.54/?0.11 ns t ooceck /t ockoce oce pin setup/hold with respec t to clk 0.22/?0.05 0.22/?0.05 ns t osrck /t ocksr sr pin setup/hold with respec t to clk 0.71/?0.29 0.71/?0.29 ns t otck /t ockt t1/t2 pins setup/hold with res pect to clk 0.56/?0.10 0.56/?0.10 ns t otceck /t ocktce tce pin setup/hold with respec t to clk 0.21/?0.05 0.21/?0.05 ns combinatorial t doq d1 to oq out or t1 to tq out 1.01 1.01 ns sequential delays t ockq clk to oq/tq out 0.71 0.71 ns t rq sr pin to oq/tq out 1.05 1.05 ns t gsrq global set/reset to q outputs 10.51 10.51 ns set/reset t rpw minimum pulse width, sr inputs 1.20 1.20 ns, min ta bl e 4 4 : iserdes switching characteristics symbol description speed grade units -2 -1 setup/hold for control lines t iscck_bitslip / t isckc_bitslip bitslip pin setup/hold with respect to clkdiv 0.09/0.17 0.09/0.17 ns t iscck_ce / t isckc_ce (2) ce pin setup/hold with respect to clk (for ce1) 0.27/0.04 0.27/0.04 ns t iscck_ce2 / t isckc_ce2 (2) ce pin setup/hold with respect to clkdiv (for ce2) ?0 .06/0.31 ?0.06/0.31 ns setup/hold for data lines t isdck_d /t isckd_d d pin setup/hold with respec t to clk 0.09/0.11 0.09/0.11 ns t isdck_ddly /t isckd_ddly ddly pin setup/hold with respect to clk (using iodelay) (1) 0.14/0.07 0.14/0.07 ns t isdck_d_ddr /t isckd_d_ddr d pin setup/hold with respect to clk at ddr mode 0.09/0.11 0.09/0.11 ns t isdck_ddly_ddr t isckd_ddly_ddr d pin setup/hold with respect to clk at ddr mode (using iodelay) (1) 0.14/0.07 0.14/0.07 ns sequential delays t iscko_q clkdiv to out at q pin 0.75 0.75 ns propagation delays t isdo_do d input to do output pin 0.25 0.25 ns notes: 1. recorded at 0 tap value. 2. t iscck_ce2 and t isckc_ce2 are reported as t iscck_ce /t isckc_ce in a trace report.
virtex-6 cxt family data sheet ds153 (v1.6) february 11, 2011 www.xilinx.com product specification 33 output serializer/deserializ er switching characteristics ta bl e 4 5 : oserdes switching characteristics symbol description speed grade units -2 -1 setup/hold t osdck_d /t osckd_d d input setup/hold with respect to clkdiv 0.31/?0.12 0.31/?0.12 ns t osdck_t /t osckd_t (1) t input setup/hold with respect to clk 0.56/?0.08 0.56/?0.08 ns t osdck_t2 /t osckd_t2 (1) t input setup/hold with respect to clkdiv 0.31/?0.08 0.31/?0.08 ns t oscck_oce /t osckc_oce oce input setup/hold with respect to clk 0.22/?0.05 0.22/?0.05 ns t oscck_s sr (reset) input setup with respect to clkdiv 0.07 0.07 ns t oscck_tce /t osckc_tce tce input setup/hold with respect to clk 0.21/?0.05 0.21/?0.05 ns sequential delays t oscko_oq clock to out from clk to oq 0.82 0.82 ns t oscko_tq clock to out from clk to tq 0.82 0.82 ns combinatorial t osdo_ttq t input to tq out 0.97 0.97 ns notes: 1. t osdck_t2 and t osckd_t2 are reported as t osdck_t /t osckd_t in the trace report.
virtex-6 cxt family data sheet ds153 (v1.6) february 11, 2011 www.xilinx.com product specification 34 input/output delay swit ching characteristics clb switching characteristics ta bl e 4 6 : input/output delay switching characteristics symbol description speed grade units -2 -1 idelayctrl t dlycco_rdy reset to ready for idelayctrl 3 3 s f idelayctrl_ref refclk frequency 200 200 mhz idelayctrl_ref_precision re fclk precision 10 10 mhz t idelayctrl_rpw minimum reset pulse width 50 50 ns iodelay t idelayresolution iodelay chain delay resolution 1/(32 x 2 x f ref ) ps t idelaypat_jit pattern dependent period jitter in delay chain for clock pattern. (1) 00ps per tap pattern dependent period jitter in delay chain for random data pattern. (2) 5 5 ps per tap pattern dependent period jitter in delay chain for random data pattern. (3) 9 9 ps per tap t iodelay_clk_max maximum frequency of clk input to iodelay 300 300 mhz t iodcck_ce / t iodckc_ce ce pin setup/hold with respec t to ck 0.65/?0.09 0.65/?0.09 ns t iodck_inc / t iodckc_inc inc pin setup/hold with respec t to ck 0.31/?0.00 0.31/?0.00 ns t iodcck_rst / t iodckc_rst rst pin setup/hold with respect to ck 0.69/?0.08 0.69/?0.08 ns t ioddo_t tscontrol delay to muxe/muxf switching and through iodelay note 4 note 4 ps t ioddo_idatain propagation delay through iodelay note 4 note 4 ps t ioddo_odatain propagation delay through iodelay note 4 note 4 ps notes: 1. when high_performance mode is set to true or false. 2. when high_performance mode is set to true 3. when high_performance mode is set to false. 4. delay depends on iodelay tap setting. see the trace report for actual values. ta bl e 4 7 : clb switching characteristics symbol description speed grade units -2 -1 combinatorial delays t ilo an ? dn lut address to a 0.08 0.08 ns, max an ? dn lut address to amux/cmux 0.23 0.25 ns, max an ? dn lut address to bmux_a 0.37 0.41 ns, max t ito an ? dn inputs to a ? d q outputs 0.79 0.91 ns, max t axa ax inputs to amux output 0.42 0.48 ns, max t axb ax inputs to bmux output 0.47 0.53 ns, max t axc ax inputs to cmux output 0.52 0.60 ns, max t axd ax inputs to dmux output 0.55 0.63 ns, max
virtex-6 cxt family data sheet ds153 (v1.6) february 11, 2011 www.xilinx.com product specification 35 t bxb bx inputs to bmux output 0.39 0.45 ns, max t bxd bx inputs to dmux output 0.50 0.58 ns, max t cxb cx inputs to cmux output 0.34 0.38 ns, max t cxd cx inputs to dmux output 0.40 0.45 ns, max t dxd dx inputs to dmux output 0.38 0.44 ns, max t opcya an input to cout ou tput 0.42 0.47 ns, max t opcyb bn input to cout ou tput 0.42 0.47 ns, max t opcyc cn input to cout output 0.35 0.39 ns, max t opcyd dn input to cout output 0.33 0.37 ns, max t axcy ax input to cout output 0.33 0.38 ns, max t bxcy bx input to cout output 0.28 0.32 ns, max t cxcy cx input to cout output 0.20 0.23 ns, max t dxcy dx input to cout output 0.19 0.22 ns, max t byp cin input to cout output 0.08 0.09 ns, max t cina cin input to amux output 0.28 0.32 ns, max t cinb cin input to bmux output 0.29 0.34 ns, max t cinc cin input to cmux output 0.30 0.34 ns, max t cind cin input to dmux output 0.33 0.38 ns, max sequential delays t cko clock to aq ? dq outputs 0.39 0.44 ns, max t shcko clock to amux ? dmux outputs 0.47 0.54 ns, max setup and hold times of clb fl ip-flops before/after clock clk t dick /t ckdi a ? d input to clk on a ? d flip flops 0.43/0.20 0.50/0.23 ns, min t ceck_clb / t ckce_clb ce input to clk on a ? d flip flops 0.32/?0.01 0.37/?0.01 ns, min t srck /t cksr sr input to clk on a ? d flip flops 0.52/?0.08 0.60/?0.08 ns, min t cinck /t ckcin cin input to clk on a ? d flip flops 0.24/0.17 0.27/0.19 ns, min set/reset t srmin sr input minimum pulse width 0.97 0.97 ns, min t rq delay from sr input to aq ? dq flip-flops 0.68 0.78 ns, max t ceo delay from ce input to aq ? dq flip-flops 0.59 0.67 ns, max f tog toggle frequency (for export control) 1098.00 1098.00 mhz notes: 1. a zero ?0? hold time listing indicates no hold time or a negative hold time. negative values can not be guaranteed ?best-case ?, but if a ?0? is listed, there is no positive hold time. 2. these items are of interest for carry chain applications. ta bl e 4 7 : clb switching characteristics (cont?d) symbol description speed grade units -2 -1
virtex-6 cxt family data sheet ds153 (v1.6) february 11, 2011 www.xilinx.com product specification 36 clb distributed ram switching characteristics (slicem only) clb shift register switching characteristics (slicem only) ta bl e 4 8 : clb distributed ram swit ching characteristics symbol description speed grade units -2 -1 sequential delays t shcko clock to a ? b outputs 1.36 1.56 ns, max t shcko_1 clock to amux ? bmux outputs 1.71 1.96 ns, max setup and hold times before/after clock clk t ds /t dh a ? d inputs to clk 0.88/0.22 1.01/0.26 ns, min t as /t ah address an inputs to clock 0.27/0.70 0.31/0.80 ns, min t ws /t wh we input to clock 0.40/?0.01 0.46/0.00 ns, min t ceck /t ckce ce input to clk 0.41/ ?0.02 0.48/?0.01 ns, min clock clk t mpw minimum pulse width 1.00 1.15 ns, min t mcp minimum clock period 2.00 2.30 ns, min notes: 1. a zero ?0? hold time listing indicates no hold time or a negative hold time. negative values cannot be guaranteed ?best-case? , but if a ?0? is listed, there is no positive hold time. 2. t shcko also represents the clk to xmux output. refer to the trace report for the clk to xmux path. ta bl e 4 9 : clb shift register switching characteristics symbol description speed grade units -2 -1 sequential delays t reg clock to a ? d outputs 1.58 1.82 ns, max t reg_mux clock to amux ? dmux output 1.93 2.22 ns, max t reg_m31 clock to dmux output via m31 output 1.55 1.78 ns, max setup and hold times before/after clock clk t ws /t wh we input 0.09/?0.01 0.10/0.00 ns, min t ceck /t ckce ce input to clk 0.10/ ?0.02 0.11/?0.01 ns, min t ds /t dh a ? d inputs to clk 0.94/0.24 1.08/0.28 ns, min clock clk t mpw minimum pulse width 0.85 0.98 ns, min notes: 1. a zero ?0? hold time listing indicates no hold time or a negative hold time. negative values cannot be guaranteed ?best-case? , but if a ?0? is listed, there is no positive hold time.
virtex-6 cxt family data sheet ds153 (v1.6) february 11, 2011 www.xilinx.com product specification 37 block ram and fifo switching characteristics ta bl e 5 0 : block ram and fifo switching characteristics symbol description speed grade units -2 -1 block ram and fifo clock-to-out delays t rcko_do and t rcko_do_reg (1) clock clk to dout output (without output register) (2)(3) 2.08 2.39 ns, max clock clk to dout output (with output register) (4)(5) 0.75 0.86 ns, max t rcko_do_ecc and t rcko_do_ecc_reg clock clk to dout output with ecc (without outpu t register) (2)(3) 3.30 3.79 ns, max clock clk to dout output with ecc (with output register) (4)(5) 0.86 0.98 ns, max t rcko_casc and t rcko_casc_reg clock clk to dout output with cascade (without outpu t register) (2) 3.18 3.65 ns, max clock clk to dout output with cascade (with output register) (4) 1.58 1.81 ns, max t rcko_flags clock clk to fifo flags outputs (6) 0.91 1.05 ns, max t rcko_pointers clock clk to fifo pointers outputs (7) 1.09 1.25 ns, max t rcko_rdcount clock clk to fifo read counter 1.09 1.25 ns, max t rcko_wrcount clock clk to fifo write counter 1.09 1.25 ns, max t rcko_sdbit_ecc and t rcko_sdbit_ecc_reg clock clk to biterr (with output register) 0.76 0.87 ns, max clock clk to biterr (without output register) 2.84 3.26 ns, max t rcko_parity_ecc clock clk to eccparity in ecc encode only mode 1.06 1.21 ns, max t rcko_rdaddr_ecc and t rcko_rdaddr_ecc_reg clock clk to rdaddr output with ecc (wit hout output register) 0.90 1.03 ns, max clock clk to rdaddr output with ecc (wit h output register) 0.92 1.06 ns, max setup and hold times before/after clock clk t rcck_addr /t rckc_addr addr inputs (8) 0.62/0.32 0.72/0.37 ns, min t rdck_di /t rckd_di din inputs (9) 1.11/0.34 1.28/0.39 ns, min t rdck_di_ecc /t rckd_di_ecc din inputs with block ram ecc in standard mode (9) 0.59/0.34 0.68/0.39 ns, min din inputs with block ram ecc encode only (9) 0.85/0.34 0.97/0.39 ns, min din inputs with fifo ecc in standard mode (9) 1.02/0.34 1.17/0.39 ns, min t rcck_clk /t rckc_clk inject single/double bit error in ecc mode 1.20/0.29 1.38/0.33 ns, min t rcck_rden /t rckc_rden block ram enable (en) input 0.41/0.30 0.47/0.34 ns, min t rcck_regce /t rckc_regce ce input of output regist er 0.22/0.31 0.25/0.35 ns, min t rcck_rstreg /t rckc_rstreg synchronous rstreg input 0.28/0.26 0.32/0.29 ns, min t rcck_rstram /t rckc_rstram synchronous rstram input 0.41/0.27 0.47/0.31 ns, min t rcck_we /t rckc_we write enable (we) input (block ram only) 0.52/0.35 0.60/0.40 ns, min t rcck_wren /t rckc_wren wren fifo inputs 0.55/0.30 0.64/0.34 ns, min t rcck_rden /t rckc_rden rden fifo inputs 0.55/0.30 0.63/0.34 ns, min reset delays t rco_flags reset rst to fifo flags/pointers (10) 1.10 1.27 ns, max t rcck_rstreg /t rckc_rstreg fifo reset timing (11) 0.28/0.26 0.32/0.29 ns, min
virtex-6 cxt family data sheet ds153 (v1.6) february 11, 2011 www.xilinx.com product specification 38 maximum frequency f max block ram (write first and no change modes) 400 350 mhz block ram (read first mode) 400 347 mhz block ram (sdp mode) (12) 400 347 mhz f max_cascade block ram cascade (write first and no change modes) 400 347 mhz block ram cascade (read first mode) 350 304 mhz f max_fifo fifo in all modes 400 350 mhz f max_ecc block ram and fifo in ecc configuration 325 282 mhz notes: 1. trace will report all of these parameters as t rcko_do . 2. t rcko_dor includes t rcko_dow , t rcko_dopr , and t rcko_dopw as well as the b port equivalent timing parameters. 3. these parameters also apply to synchronous fifo with do_reg = 0. 4. t rcko_do includes t rcko_dop as well as the b port equivalent timing parameters. 5. these parameters also apply to multirate (asynchronous) and synchronous fifo with do_reg = 1. 6. t rcko_flags includes the following parameters: t rcko_aempty , t rcko_afull , t rcko_empty , t rcko_full , t rcko_rderr , t rcko_wrerr. 7. t rcko_pointers includes both t rcko_rdcount and t rcko_wrcount. 8. the addr setup and hold must be met when en is asserted (even when we is deasserted) . otherwise, block ram data corruption is possible. 9. t rcko_di includes both a and b inputs as well as the parity inputs of a and b. 10. t rco_flags includes the following flags: aempty, afull, em pty, full, rderr, wrerr, rdcount, and wrcount. 11. the fifo reset must be asserted for at least three positive clock edges. 12. when using ise software v12.4 or later, if the rdarrdr_collision_hwconfig attribute is set to performance or the block ram is in single-port operation, then the faster f max for write_first/no_change modes apply. ta bl e 5 0 : block ram and fifo switching characteristics (cont?d) symbol description speed grade units -2 -1
virtex-6 cxt family data sheet ds153 (v1.6) february 11, 2011 www.xilinx.com product specification 39 dsp48e1 switching characteristics ta bl e 5 1 : dsp48e1 switching characteristics symbol description speed grade units -2 -1 setup and hold times of data/control pins to the input register clock t dspdck_{a, acin; b, bcin}_{areg; breg} / t dspckd_{a, acin; b, bcin}_{areg; breg} {a, acin, b, bcin} input to {a, b} register clk 0. 35/0.34 0.41/0.39 ns t dspdck_c_creg /t dspckd_c_creg c input to c register clk 0.22/0.24 0.26/0.27 ns t dspdck_d_dreg /t dspckd_d_dreg d input to d register clk 0.15/0.39 0.17/0.44 ns setup and hold times of data pins to the pipeline register clock t dspdck_{a, acin, b, bcin}_preg_mult / t dspckd_{a, acin, b, bcin}_preg_mult {a, acin, b, bcin} input to m register clk 3.21/0.02 3.69/0.02 ns t dspdck_{a, d}_adreg / t dspckd _ {a, d}_adreg {a, d} input to ad regist er clk 1.69/0.13 1.94/0.15 ns setup and hold times of data/control pins to the output register clock t dspdck_{a, acin, b, bcin}_preg_mult / t dspckd_{a, acin, b, bcin}_preg_mult {a, acin, b, bcin} input to p register clk using multiplier 5.20/?0.19 5.97/?0.22 ns t dspdck_d_dreg_mult / t dspckd_d_dreg_mult d input to p register clk 4.90/?0.65 5.63/?0.75 ns t dspdck_{a, acin, b, bcin}_preg / t dspckd_{a, acin, b, bcin}_preg {a, acin, b, bcin} inpu t to p register clk not using multiplier 2.15/?0.19 2.47/?0.22 ns t dspdck_c_preg / t dspckd_c_preg c input to p register clk 1.91/?0.14 2.19/?0.17 ns t dspdck_{pcin, carrycascin, multsignin}_preg / t dspckd_{pcin, carrycasc in, multsignin}_preg {pcin, carrycascin, multsignin} input to p register clk 1.67/?0.04 1.92/?0.05 ns setup and hold times of the ce pins t dspdck_{cea; ceb}_{areg; breg} / t dspckd_{cea; ceb}_{areg; breg} {cea; ceb} input to {a; b} r egister clk 0.22/0.25 0.25/0.29 ns t dspdck_cec_creg / t dspckd_cec_creg cec input to c register clk 0.24/0.23 0.28/0.27 ns t dspdck_ced_dreg / t dspckd_ced_dreg ced input to d register clk 0.31/0.14 0.35/0.16 ns t dspdck_cem_mreg / t dspckd_cem_mreg cem input to m register clk 0.26/0.25 0.30/0.28 ns t dspdck_cep_preg / t dspckd_cep_preg cep input to p register clk 0.46/0.03 0.53/0.03 ns setup and hold times of the rst pins t dspdck_{rsta; rstb}_{areg; breg} / t dspckd_{rsta; rstb}_{areg; breg} {rsta, rstb} input to {a, b} r egister clk 0.38/0.22 0.43/0.25 ns t dspdck _rstc_creg / t dspckd _rstc_creg rstc input to c register clk 0.23/0.09 0.27/0.11 ns t dspdck _rstd_dreg / t dspckd _rstd_dreg rstd input to d register clk 0.38/0.19 0.44/0.21 ns t dspdck _rstm_mreg / t dspckd _rstm_mreg rstm input to m register clk 0.26/0.30 0.30/0.35 ns t dspdck _rstp_preg / t dspckd _rstp_preg rstp input to p register clk 0.33/0.05 0.41/0.06 ns combinatorial delays from input pins to output pins t dspdo_{a, b}_{p, carryout}_mult {a, b} input to {p, carryout} output using multiplier 5.08 5.84 ns t dspdo_d_{p, carryout}_mult d input to {p, carryout} output using multiplier 4.82 5.54 ns t dspdo_{a, b}_{p, carryout} {a, b} input to {p, carryout} output not using multiplier 2.07 2.38 ns t dspdo_{c, carryin}_{p, carryout} {c, carryin} input to {p , carryout} output 1.83 2.10 ns
virtex-6 cxt family data sheet ds153 (v1.6) february 11, 2011 www.xilinx.com product specification 40 combinatorial delays from input pins to cascading output pins t dspdo_{a; b}_{acout; bcout} {a, b} input to {acout, bcout} output 0.65 0.75 ns t dspdo_{a, b}_{pcout, carrycascout, multsignout}_mult {a, b} input to {pcout, carrycascout, multsignout} output using multiplier 5.24 6.03 ns t dspdo_d_{pcout, carrycascout, multsignout}_mult d input to {pcout, carrycascout, multsignout} output using multiplier 4.94 5.68 ns t dspdo_{a, b}_{pcout, carrycascout, multsignout} {a, b} input to {pcout, carrycascout, multsignout} output not using multiplier 2.19 2.52 ns t dspdo__{c, carryin}_{pcout, carrycascout,multsignout} {c, carryin} input to {pcout, carrycascout, multsignout} output 1.95 2.25 ns combinatorial delays from cascading input pins to all output pins t dspdo_{acin, bcin}_{p, carryout}_mult {acin, bcin} input to {p, carryout} output using multiplier 4.97 5.72 ns t dspdo_{acin, bcin}_{p, carryout {acin, bcin} input to {p, carryout} output not using multiplier 1.92 2.21 ns t dspdo_{acin; bcin}_{acout; bcout} {acin, bcin} input to {acout, bcout} output 0.49 0.57 ns t dspdo_{acin, bcin}_{p cout, carrycascout, multsignout}_mult {acin, bcin} input to {pcout, carrycascout, multsignout} output using multiplier 5.10 5.86 ns t dspdo_{acin, bcin}_{p cout, carrycascout, multsignout} {acin, bcin} input to {pcout, carrycascout, multsignout} output not using multiplier 2.05 2.35 ns t dspdo_{pcin, carrycascin, multsignin}_ {p, carryout} {pcin, carrycascin, multsignin} input to {p, carryout} output 1.60 1.83 ns t dspdo_{pcin, carrycascin , multsignin}_ {pcout, carrycascout, multsignout} {pcin, carrycascin, multsignin} input to {pcout, carrycascout, multsignout} output 1.72 1.98 ns clock to outs from output re gister clock to output pins t dspcko_{p, carryout}_preg clk (preg) to {p, carryout} output 0.50 0.57 ns t dspcko_{pcout, carrycascout, multsignout}_preg clk (preg) to {carrycascout, pcout, multsignout} output 0.50 0.66 ns clock to outs from pipeline register clock to output pins t dspcko_{p, carryout}_mreg clk (mreg) to {p, carryout} output 2.30 2.65 ns t dspcko_{pcout, carrycascout, multsignout}_mreg clk (mreg) to {pcout, carrycascout, multsignout} output 2.43 2.79 ns t dspcko_{p, carryout}_adreg_mult clk (adreg) to {p, carryout} output 3.72 4.72 ns t dspcko_{pcout, carrycascout, multsignout}_adreg_mult clk (adreg) to {pcout, carrycascout, multsignout} output 3.84 4.42 ns clock to outs from input register clock to output pins t dspcko_{p, carryout }_{areg, breg}_mult clk (areg, breg) to {p, carryout} output using multiplier 5.36 6.16 ns t dspcko_{p, carryout}_{areg, breg} clk (areg, breg) to {p, carryout} output not using multiplier 2.27 2.61 ns t dspcko_{p, carryout}_creg clk (creg) to {p, carryout} output 2.27 2.61 ns t dspcko_{p, carryout}_dreg_mult clk (dreg) to {p, carryout} output 5.25 6.04 ns ta bl e 5 1 : dsp48e1 switching characteristics (cont?d) symbol description speed grade units -2 -1
virtex-6 cxt family data sheet ds153 (v1.6) february 11, 2011 www.xilinx.com product specification 41 clock to outs from input regist er clock to cascad ing output pins t dspcko_{acout; bcout}_{areg; breg} clk (areg, breg) to {p, carryout} output 0.89 1.02 ns t dspcko_{pcout, carrycascout, multsignout}_{areg, breg}_mult clk (areg, breg) to {pcout, carrycascout, multsignout} output using multiplier 5.49 6.31 ns t dspcko_{pcout, carrycascout, multsignout}_{areg, breg} clk (areg, breg) to {pcout, carrycascout, multsignout} output not using multiplier 2.40 2.76 ns t dspcko_{pcout, carrycascout, multsignout}_dreg_mult clk (dreg) to {pcout, carrycascout, multsignout} output using multiplier 5.38 6.18 ns t dspcko_{pcout, carrycascout, multsignout}_creg clk (creg) to {pcout, carrycascout, multsignout} output 2.40 2.76 ns maximum frequency f max with all registers used 350 275 mhz f max_patdet with pattern detector 350 275 mhz f max_mult_nomreg two register multiply without mreg 262 227 mhz f max_mult_nomreg_patdet two register multiply without mreg with pattern detect 241 209 mhz f max_preadd_mult_noadreg without adreg 292 253 mhz f max_preadd_mult_noadreg_patdet without adreg with pattern detect 292 253 mhz f max_nopipelinereg without pipeline registers (mreg, adreg) 196 170 mhz f max_nopipelinereg_patdet without pipeline registers (mreg, adreg) with pattern detect 184 160 mhz ta bl e 5 1 : dsp48e1 switching characteristics (cont?d) symbol description speed grade units -2 -1
virtex-6 cxt family data sheet ds153 (v1.6) february 11, 2011 www.xilinx.com product specification 42 configuration switching characteristics ta bl e 5 2 : configuration switching characteristics symbol description speed grade units -2 -1 power-up timing characteristics t pl (1) program latency 3 3 ms, max t por (1) power-on-reset 15/55 15/55 ms, min/max t icck cclk (output) delay 400 400 ns, min t program program pulse width 250 250 ns, min master/slave serial mode programming switching (1) t dcck /t cckd din setup/hold, slave mode 4.0/0.0 4.0/0.0 ns, min t dscck /t scckd din setup/hold, master mode 4.0/0.0 4.0/0.0 ns, min t cco dout at 2.5v 6 6 ns, max dout at 1.8v 6 6 ns, max f mcck maximum cclk frequency, serial modes 100 100 mhz, max f mccktol frequency tolerance, master mode with respect to nominal cclk 55 55 % f mscck slave mode external cclk 100 100 mhz selectmap mode programming switching t smdcck /t smcckd selectmap data setup/hold 4.0/0.0 4.0/0.0 ns, min t smcscck /t smcckcs csi_b setup/hold 4.0/0.0 4.0/0.0 ns, min t smcckw /t smwcck rdwr_b setup/hold 10.0/0.0 10.0/0.0 ns, min t smckcso cso_b clock to out (330 ? pull-up resistor required) 77ns, min t smco cclk to data out in readback at 2.5v 8 8 ns, max cclk to data out in readback at 1.8v 8 8 ns, max t smckby cclk to busy out in readback at 2.5v 6 6 ns, max cclk to busy out in readback at 1.8v 6 6 ns, max f smcck maximum frequency with respect to nominal cclk 100 100 mhz, max f rbcck maximum readback frequency with respect to nominal cclk 100 100 mhz, max f mccktol frequency tolerance with respect to nominal cclk 55 55 % boundary-scan port timing specifications t taptck /t tcktap tms and tdi setup time befo re tck/ hold time after tck 3.0/2.0 3.0/2.0 ns, min t tcktdo tck falling edge to tdo output valid at 2.5v 6 6 ns, max tck falling edge to tdo output valid at 1.8v 6 6 ns, max f tck maximum configuration tck clock frequency 66 66 mhz, max f tckb_min minimum boundary-scan tck clock frequency when using ieee std 1149.6 (ac-jt ag). minimum operating temperature for ieee std 1149.6 is 0c. 15 15 mhz, min f tckb maximum boundary-scan tck clock frequency 66 66 mhz, max
virtex-6 cxt family data sheet ds153 (v1.6) february 11, 2011 www.xilinx.com product specification 43 bpi master flash mode programming switching t bpicco (2) addr[25:0], rs[1:0], fcs_ b, foe_b, fwe_b outputs valid after cclk rising edge at 2.5v 66 ns addr[25:0], rs[1:0], fcs_ b, foe_b, fwe_b outputs valid after cclk rising edge at 1.8v 66 ns t bpidcc /t bpiccd setup/hold on d[15:0] data input pins 4.0/0.0 4.0/0.0 ns t initaddr minimum period of initial addr [25:0] address cycles 3 3 cclk cycles spi master flash mode programming switching t spidcc /t spidccd din setup/hold before/after the rising cclk edge 3.0/0.0 3.0/0.0 ns t spiccm mosi clock to out at 2.5v 6 6 ns mosi clock to out at 1.8v 6 6 ns t spiccfc fcs_b clock to out at 2.5v 6 6 ns fcs_b clock to out at 1.8v 6 6 ns t fsinit /t fsinith fs[2:0] to init_b rising edge setup and hold 2 2 s cclk output (master modes) t mcckl master cclk clock low time duty cycle 45/55 45/55 %, min/max t mcckh master cclk clock high time duty cycle 45/55 45/55 %, min/max cclk input (slave modes) t scckl slave cclk clock minimum low time 2.5 2.5 ns, min t scckh slave cclk clock minimum high time 2.5 2.5 ns, min dynamic reconfiguration port (drp) for mmcm before and after dclk f dck maximum frequency for dclk 200 200 mhz t mmcmdck_daddr / t mmcmckd_daddr daddr setup/hold 1.63/0.00 1.63/0.00 ns t mmcmdck_di /t mmcmckd_di di setup/hold 1.63/0.00 1.63/0.00 ns t mmcmdck_den /t mmcmckd_den den setup/hold time 1.63/0.00 1.63/0.00 ns t mmcmdck_dwe /t mmcmckd_dwe dwe setup/hold time 1.63/0.00 1.63/0.00 ns t mmcmcko_do clk to out of do (3) 3.64 3.64 ns t mmcmcko_drdy clk to out of drdy 0.38 0.38 ns notes: 1. to support longer delays in configuration, use the design solutions described in virtex-6 fpga configuration guide . 2. only during configuration, the last edge is determined by a weak pull-up/pull-down resistor in the i/o. 3. do will hold until next drp operation. ta bl e 5 2 : configuration switching characteristics (cont?d) symbol description speed grade units -2 -1
virtex-6 cxt family data sheet ds153 (v1.6) february 11, 2011 www.xilinx.com product specification 44 clock buffers and networks ta bl e 5 3 : global clock switching characte ristics (incl uding bufgctrl) symbol description speed grade units -2 -1 t bccck_ce /t bcckc_ce (1) ce pins setup/hold 0.16/0.00 0.16/0.00 ns t bccck_s /t bcckc_s (1) s pins setup/hold 0.16/0.00 0.16/0.00 ns t bccko_o (2) bufgctrl delay from i0/i1 to o 0.10 0.10 ns maximum frequency f max global clock tree (bufg) 700 700 mhz notes: 1. t bccck_ce and t bcckc_ce must be satisfied to assure glitch-free operation of the global clock when switching between clocks. these parameters do not apply to the bufgmux_virtex4 primitive that assures glitch-free operation. the other global clock setup and h old times are optional; only needing to be satisfied if device operation requires simulation matches on a cycle-for-cycle basis whe n switching between clocks. 2. t bgcko_o (bufg delay from i0 to o) values are the same as t bccko_o values. ta bl e 5 4 : input/output clock switching characteristics (bufio) symbol description speed grade units -2 -1 t biocko_o clock to out delay from i to o 0.18 0.18 ns maximum frequency f max i/o clock tree (bufio) 710 710 mhz
virtex-6 cxt family data sheet ds153 (v1.6) february 11, 2011 www.xilinx.com product specification 45 mmcm switching characteristics ta bl e 5 5 : regional clock switching characteristics (bufr) symbol description speed grade units -2 -1 t brcko_o clock to out delay from i to o 0.75 0.75 ns 0.75 0.75 ns 0.75 0.75 ns 0.75 0.75 ns t brcko_o_byp clock to out delay from i to o with divide bypass attribute set 0.37 0.37 ns 0.37 0.37 ns 0.37 0.37 ns 0.37 0.37 ns t brdo_o propagation delay from clr to o 0.83 0.83 ns maximum frequency f max regional clock tree (bufr) 300 300 mhz ta bl e 5 6 : horizontal clock buffer switching characteristics (bufh) symbol description speed grade units -2 -1 t bhcko_o bufh delay from i to o 0.13 0.13 ns t bhcck_ce /t bhckc_ce ce pin setup and hold 0.05/0.05 0.05/0.05 ns maximum frequency f max horizontal clock buffer (bufh) 700 700 mhz ta bl e 5 7 : mmcm specification symbol description speed grade units -2 -1 f inmax maximum input clock frequency (1) 700 700 mhz f inmin minimum input clock frequency 10 10 mhz f injitter maximum input clock period jitter < 20% of clock input period or 1 ns max f induty allowable input duty cycle: 10?49 mhz 25/75 % allowable input duty cycle: 50?199 mhz 30/70 % allowable input duty cycle: 200?399 mhz 35/65 % allowable input duty cycle: 400?499 mhz 40/60 % allowable input duty cycle: >500 mhz 45/55 % f min_psclk minimum dynamic phase shift clock frequency 0.01 0.01 mhz f max_psclk maximum dynamic phase shift clock frequency 450 450 mhz f vcomin minimum mmcm vco frequency 600 600 mhz f vcomax maximum mmcm vco frequency 1200 1200 mhz f bandwidth low mmcm bandwidth at typical (2) 1.00 1.00 mhz high mmcm bandwidth at typical (2) 4.00 4.00 mhz
virtex-6 cxt family data sheet ds153 (v1.6) february 11, 2011 www.xilinx.com product specification 46 t statphaoffset static phase offset of the mmcm outputs (3) 0.12 0.12 ns t outjitter mmcm output jitter (4) note 1 t outduty mmcm output clock duty cycle precision (5) 0.20 0.20 ns t lockmax mmcm maximum lock time 100 100 s f outmax mmcm maximum output frequency 700 700 mhz f outmin mmcm minimum output frequency (6)(7) 4.69 4.69 mhz t extfdvar external clock feedback variation < 20% of clock input period or 1 ns max rst minpulse minimum reset pulse width 1.5 1.5 ns f pfdmax maximum frequency at the phase frequency detector with bandwidth set to high or optimized (8) 450 450 mhz maximum frequency at the phase frequency detector with bandwidth set to low 300 300 mhz f pfdmin minimum frequency at the phase frequency detector with bandwidth set to high or optimized 135 135 mhz minimum frequency at the phase frequency detector with bandwidth set to low 10.00 10.00 mhz t fbdelay maximum delay in the feedback path 3 ns max or one clkin cycle t mmcmdck_psen / t mmcmckd_psen setup and hold of phase shift enable 1.04/0.00 1.04/0.00 ns t mmcmdck_psincdec / t mmcmckd_psincdec setup and hold of phase shift incr ement/decrement 1.04/0.00 1.04/0.00 ns t mmcmcko_psdone phase shift clock-to-out of psdone 0.38 0.38 ns notes: 1. when divclk_divide = 3 or 4, f inmax is 315 mhz. 2. the mmcm does not filter typical spread-spectrum input clocks because they are usually far below the bandwidth filter frequen cies. 3. the static offset is measured between any mmcm outputs with identical phase. 4. values for this parameter are available in the architecture wizard. 5. includes global clock buffer. 6. calculated as f vco /128 assuming output duty cycle is 50%. 7. when cascade4_out = true, f outmin is 0.036 mhz. 8. in ise software 12.3 (or earlier versions supporting the virtex-6 family), the phase frequency detector optimized bandwidth s etting is equivalent to the high bandwidth setting. starting with ise software 12.4, the optimized bandwidth setting is automatically adj usted to low when the software can determine that the phase frequency detector input is less than 135 mhz. ta bl e 5 7 : mmcm specification (cont?d) symbol description speed grade units -2 -1
virtex-6 cxt family data sheet ds153 (v1.6) february 11, 2011 www.xilinx.com product specification 47 virtex-6 cxt device pin-to-pin output parameter guidelines all devices are 100% functionally tested. the representative values for typical pin locations and normal clock loading are listed in ta bl e 5 8 . values are expressed in nanoseconds unless otherwise noted. ta bl e 5 8 : global clock input to output delay without mmcm symbol description device speed grade units -2 -1 lvcmos25 global clock input to output delay us ing output flip-flop, 12ma, fast slew rate, without mmcm. t ickof global clock input and outff without mmcm xc6vcx75t 5.88 5.88 ns XC6VCX130T 6.00 6.00 ns xc6vcx195t 6.13 6.13 ns xc6vcx240t 6.13 6.13 ns notes: 1. listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible iob and clb flip-flops are clocked by the global clock net. ta bl e 5 9 : global clock input to output delay with mmcm symbol description device speed grade units -2 -1 lvcmos25 global clock input to output delay us ing output flip-flop, 12ma, fast slew rate, with mmcm. t ickofmmcmgc global clock input and outff with mmcm xc6vcx75t 2.77 2.77 ns XC6VCX130T 2.78 2.78 ns xc6vcx195t 2.78 2.78 ns xc6vcx240t 2.79 2.79 ns notes: 1. listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible iob and clb flip-flops are clocked by the global clock net. 2. mmcm output jitter is already included in the timing calculation. ta bl e 6 0 : clock-capable clock input to output delay with mmcm symbol description device speed grade units -2 -1 lvcmos25 clock-capable clock input to output dela y using output flip-flop, 12ma, fast slew rate, with mmcm. t ickofmmcmcc clock-capable clock input and outff with mmcm xc6vcx75t 2.63 2.63 ns XC6VCX130T 2.65 2.65 ns xc6vcx195t 2.65 2.65 ns xc6vcx240t 2.65 2.65 ns notes: 1. listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible iob and clb flip-flops are clocked by the global clock net. 2. mmcm output jitter is already included in the timing calculation.
virtex-6 cxt family data sheet ds153 (v1.6) february 11, 2011 www.xilinx.com product specification 48 virtex-6 cxt device pin-to-pin input parameter guidelines all devices are 100% functionally tested. the representative values for typical pin locations and normal clock loading are listed in ta bl e 6 1 . values are expressed in nanoseconds unless otherwise noted. ta bl e 6 1 : global clock input setup and hold without mmcm symbol description device speed grade units -2 -1 input setup and hold time relative to global clock input signal for lvcmos25 standard. (1) t psfd / t phfd full delay (legacy delay or default delay) global clock input and iff (2) without mmcm xc6vcx75t 1.75/?0.01 1.75/?0.01 ns XC6VCX130T 1.88/?0.11 1.88/?0.11 ns xc6vcx195t 1.97/?0.14 1.97/?0.14 ns xc6vcx240t 1.97/?0.14 1.97/?0.14 ns notes: 1. setup and hold times are measured over worst case conditions (process, voltage, temperature). setup time is measured relative to the global clock input signal using the slowest process, highest temperature, and lowest voltage. hold time is measured relative to the global clock input signal using the fastest process, lowest temperature, and highest voltage. 2. iff = input flip-flop or latch. 3. a zero "0" hold time listing indicates no hold time or a negative hold time. negative values can not be guaranteed "best-case ", but if a "0" is listed, there is no positive hold time. ta bl e 6 2 : global clock input setup and hold with mmcm symbol description device speed grade units -2 -1 input setup and hold time relative to global clock input signal for lvcmos25 standard. (1) t psmmcmgc / t phmmcmgc no delay global clock input and iff (2) with mmcm xc6vcx75t 1.72/?0.22 1.72/?0.22 ns XC6VCX130T 1.81/?0.21 1.81/?0.21 ns xc6vcx195t 1.82/?0.20 1.82/?0.20 ns xc6vcx240t 1.82/?0.20 1.82/?0.20 ns notes: 1. setup and hold times are measured over worst case conditions (process, voltage, temperature). setup time is measured relative to the global clock input signal using the slowest process, highest temperature, and lowest voltage. hold time is measured relative to the global clock input signal using the fastest process, lowest temperature, and highest voltage. 2. iff = input flip-flop or latch. 3. use ibis to determine any duty-cycle distortion incurred using various standards. ta bl e 6 3 : clock-capable clock input setup and hold with mmcm symbol description device speed grade units -2 -1 input setup and hold time relative to clock-ca pable clock input signal for lvcmos25 standard. (1) t psmmcmcc / t phmmcmcc no delay clock-capable clock input and iff (2) with mmcm xc6vcx75t 1.86/?0.28 1.86/?0.28 ns XC6VCX130T 1.93/?0.28 1.93/?0.28 ns xc6vcx195t 1.96/?0.27 1.96/?0.27 ns xc6vcx240t 1.96/?0.27 1.96/?0.27 ns notes: 1. setup and hold times are measured over worst case conditions (process, voltage, temperature). setup time is measured relative to the global clock input signal using the slowest process, highest temperature, and lowest voltage. hold time is measured relative to the global clock input signal using the fastest process, lowest temperature, and highest voltage. 2. iff = input flip-flop or latch. 3. use ibis to determine any duty-cycle distortion incurred using various standards.
virtex-6 cxt family data sheet ds153 (v1.6) february 11, 2011 www.xilinx.com product specification 49 clock switching characteristics the parameters in this section provide the necessary values for calculating timing budgets for virtex-6 cxt fpga clock transmitter and receiver data-valid windows. ta bl e 6 4 : duty cycle distortion and clock-tree skew symbol description device speed grade units -2 -1 t dcd_clk global clock tree du ty cycle distortion (1) all 0.12 0.12 ns t ckskew global clock tree skew (2) xc6vcx75t 0.18 0.18 ns XC6VCX130T 0.29 0.29 ns xc6vcx195t 0.31 0.31 ns xc6vcx240t 0.31 0.31 ns t dcd_bufio i/o clock tree duty cycle distortion all 0.08 0.08 ns t bufioskew i/o clock tree skew across one clock region all 0.03 0.03 ns t bufioskew2 i/o clock tree skew across three clock regions all 0.22 0.22 ns t dcd_bufr regional clock tree duty cycl e distortion all 0.15 0.15 ns notes: 1. these parameters represent the worst-case duty cycle distortion ob servable at the pins of the de vice using lvds output buffer s. for cases where other i/o standards are used, ibis can be used to calculate any additional duty cycle distortion that might be caused by asymmetrical rise/fall times. 2. the t ckskew value represents the worst-case clock-tree skew observable between sequential i/o elements. significantly less clock-tree skew exists for i/o registers that are close to each other and fe d by the same or adjacent clock-tree branches. use the xilinx fpga_editor and timing analyzer tools to evaluate clock skew specific to your application. ta bl e 6 5 : package skew symbol description device package value units t pkgskew package skew (1) xc6vcx75t ff484 ps ff784 ps XC6VCX130T ff484 95 ps ff784 146 ps ff1156 165 ps xc6vcx195t ff784 ps ff1156 ps xc6vcx240t ff784 146 ps ff1156 182 ps notes: 1. these values represent the worst-case skew between any two selectio resources in the package: shortest flight time to longest flight time from pad to ball (7.0 ps per mm). 2. package trace length information is available for these device/package combinations. this information can be used to deskew t he package.
virtex-6 cxt family data sheet ds153 (v1.6) february 11, 2011 www.xilinx.com product specification 50 revision history the following table shows the revision history for this document: ta bl e 6 6 : sample window symbol description device speed grade units -2 -1 t samp sampling error at receiver pins (1) all 610 610 ps t samp_bufio sampling error at receiver pins using bufio (2) all 400 400 ps notes: 1. this parameter indicates the total sampling error of virtex-6 cxt fpga ddr input registers, measured across voltage, temperat ure, and process. the characterization methodology uses the mmcm to captur e the ddr input registers? edges of operation. these measureme nts include: - clk0 mmcm jitter - mmcm accuracy (phase offset) - mmcm phase shift resolution these measurements do not include package or clock tree skew. 2. this parameter indicates the total sampling error of virtex-6 cxt fpga ddr input registers, measured across voltage, temperat ure, and process. the characterization methodology uses the bufio clock network and iodelay to capture the ddr input registers? edges of operation. these measurements do not include package or clock tree skew. ta bl e 6 7 : pin-to-pin setup/hold and clock-to-out symbol description speed grade units -2 -1 data input setup and hold times relative to a forwarded clock input pin using bufio t pscs /t phcs setup/hold of i/o clock ?0.33/1.31 ?0.33/1.31 ns pin-to-pin clock-to -out using bufio t ickofcs clock-to-out of i/o clock 5.19 5.19 ns date version description of revisions 07/08/09 1.0 initial xilinx release. 02/05/10 1.1 removed figure 11: placement diagram for th e ff1156 package (5 of 5) from page 11 as there are only 16 gtx transceivers in the ff1156 package. corrected the placement diagrams in figure 2 through figure 10 .
virtex-6 cxt family data sheet ds153 (v1.6) february 11, 2011 www.xilinx.com product specification 51 06/08/10 1.2 revised gtx transceivers in cxt devices, page 5 . added v fs and revised the v in and v ts values in table 9, page 11 . added v fs and note 6 to ta bl e 1 0 . revised description of c in in ta bl e 1 1 , including adding note 3. updated ta b l e 1 3 including adding note 2. removed diff sstl15 and added values to sstl15 in ta b l e 1 5 . updated ta b l e 1 6 through ta bl e 1 9 . added efuse read endurance section. updated entire gtx transceivers in cxt devices section. changed specifications of pci express in ta bl e 3 4 . in ta b l e 3 5 , removed rldram ii and revised and added values to other interface performance specifications. updated speed specification to v1 .04 with appropriate changes to ta b l e 3 6 . revised the iob switching characteristics in ta b l e 3 8 . updated values in ta b l e 3 9 and note 4 in ta bl e 4 1 . ilogic ( ta bl e 4 2 ), ologic ( ta b l e 4 3 ), iserdes ( ta b l e 4 4 ), and oserdes ( ta bl e 4 5 ) switching characteristics changes. revised t iodelay_clk_max and t idelaypat_jit in ta b l e 4 6 . revised clb switching characteristics and added t shcko to ta b l e 4 7 and revised clb switching characteristics in ta b l e 4 8 and ta b l e 4 9 . in ta b l e 5 0 , removed t rcko_rdcount and t rcko_wrcount , removed t rcko_parity_ecc : clock clk to eccparity in standard ecc mode, revised t rdck_di_ecc /t rckd_di_ecc , t rcko_pointers , and revised f max and f max_cascade switching characteristics. multiple changes to configuration specifications in ta b l e 5 2 . revised switching char acteristics and global clock tree (bufg) f max in ta bl e 5 3 . revised switching characteristi cs and i/o clock tree (bufio) f max in ta bl e 5 4 . added note 1 to ta bl e 5 5 . revised the f max horizontal clock tree (bufh) in ta bl e 5 6 . multiple changes to mmcm specifications in ta bl e 5 7 including f inmax and f outmax . updated switching characteristics in ta b l e 5 8 through ta b l e 6 3 . removed t dcd_bufh and t bufhskew from ta bl e 6 4 . 06/30/10 1.3 production release of XC6VCX130T and xc6vcx240t in ta b l e 3 6 and ta b l e 3 7 . updated -1 speed grade sdr values in ta b l e 3 5 . updated bufio f max specification in ta bl e 5 4 . added note 6 to ta b l e 5 7 . 07/28/10 1.4 production release of xc6vcx75t and xc6vcx195t in ta bl e 3 6 and ta bl e 3 7 using ise 12.2 software with speed file v1.06 using the speed file patch . updated pci compliance on page 1. added values to ta bl e 1 3 . in ta b l e 2 5 , update v cmoutdc equation to mgtavtt ? dv ppout /4. updated f max in ta bl e 5 3 , ta bl e 5 4 , and ta bl e 5 6 . updated f inmax and f outmax in ta b l e 5 7 . updated values in ta b l e 6 1 , ta bl e 6 2 , and ta b l e 6 3 . 10/14/10 1.5 moved data sheet to production status on the fi rst page. updated speed file with ise 12.3 software with speed file v1.08 using the speed file patch. in ta b l e 5 1 , updated values for t dspcko_{pcout, carrycascout, multsignout}_preg . 02/11/11 1.6 updated ta b l e 1 0 to include the industrial range specifications. added note 12 to ta bl e 5 0 . revised t bpicco values in ta bl e 5 2 . updated range description for f induty in ta b l e 5 7 and added note 8. the following revisions are due to specification changes as described in xcn11009 , virtex-6 fpga: data sheet, user guides, and jtag id updates . in ta b l e 5 2 , updated the values for t smcckw , t spidcc , t spiccm , and t spiccfc . in ta b l e 5 7 : mmcm specification , added bandwidth settings to f pfdmin and added note 1. date version description of revisions
virtex-6 cxt family data sheet ds153 (v1.6) february 11, 2011 www.xilinx.com product specification 52 notice of disclaimer the xilinx hardware fpga and cpld devices referred to herein (?products?) are subject to the terms and conditions of the xilinx limite d warranty which can be viewed at http://www.xilinx.com/warranty.htm . this limited warranty does not extend to any use of products in an application or environment that is not within the specifications stated in the xilinx data sheet. all specifications are subject to change without notice. products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance, such as life-support or safety devic es or systems, or any other application that invokes the potential risks of death, personal injury, or property or environmental damage (?critical applications?). use of products in critical applications is at the sole risk of customer, subject to applicable laws and regulations. critical applications disclaimer xilinx products (including hardware, software and/or ip cores) are no t designed or intended to be fail- safe, or for use in any application requiring fail-s afe performance, such as in life-support or safety devices or systems, class iii medical devices, nuclea r facilities, applications related to the deployment of airbags, or any other applications that could lead to death, personal injury or severe property or environmental damage (individually and collectivel y, ?critical applications?). furthermore, xilinx products are not designed or intended for use in an y applications that affect control of a vehicle or aircraft, unless there is a fail-saf e or redundancy feature (which do es not include use of software in the xilinx device to implement the redundancy) and a warning signal upon failure to the operator. customer agrees, prior to using or distributing any systems that incorporate xilinx products, to thoroughly test the same for safety purposes. to the maximum extent permitted by applicable law, customer assumes the sole risk and liability of any use of xilinx products in critical applications. automotive applications disclaimer xilinx products are not designed or intended to be fail -safe, or for use in any application requiring fail- safe performance, such as applications related to: (i) the deployment of airbags, (ii) control of a vehicle, unless there is a fail-safe or redundancy fe ature (which does not incl ude use of software in the xilinx device to implement the redundancy) and a wa rning signal upon failure to the operator, or (iii) uses that could lead to death or personal injury. cu stomer assumes the sole risk and liability of any use of xilinx products in such applications.

▲Up To Search▲

Price & Availability of XC6VCX130T

	To Download XC6VCX130T Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .